An efficient technique to select logic nodes for single event transient pulse-width reduction

Nihaar N Mahatme; Indranil Chatterjee; Akash Patki; Daniel B Limbrick; Bharat L Bhuva; Ronald D Schrimpf; William Robinson

An efficient technique to select logic nodes for single event transient pulse-width reduction

Nihaar N Mahatme, Indranil Chatterjee, Akash Patki, Daniel B Limbrick, Bharat L Bhuva, Ronald D Schrimpf, William Robinson

School of Physics

Research output: Contribution to journal › Article (Academic Journal) › peer-review

8 Citations (Scopus)

Original language	English
Pages (from-to)	114-117
Number of pages	4
Journal	Microelectronics Reliability
Volume	53
Issue number	1
Publication status	Published - 2013

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Cite this

@article{88ac14fdb594410784318f059a403134,

title = "An efficient technique to select logic nodes for single event transient pulse-width reduction",

author = "Mahatme, \{Nihaar N\} and Indranil Chatterjee and Akash Patki and Limbrick, \{Daniel B\} and Bhuva, \{Bharat L\} and Schrimpf, \{Ronald D\} and William Robinson",

year = "2013",

language = "English",

volume = "53",

pages = "114--117",

journal = "Microelectronics Reliability",

publisher = "Elsevier Limited",

number = "1",

}

TY - JOUR

T1 - An efficient technique to select logic nodes for single event transient pulse-width reduction

AU - Mahatme, Nihaar N

AU - Chatterjee, Indranil

AU - Patki, Akash

AU - Limbrick, Daniel B

AU - Bhuva, Bharat L

AU - Schrimpf, Ronald D

AU - Robinson, William

PY - 2013

Y1 - 2013

M3 - Article (Academic Journal)

VL - 53

SP - 114

EP - 117

JO - Microelectronics Reliability

JF - Microelectronics Reliability

IS - 1

ER -