An evaluation of hash functions on a power analysis resistant processor architecture

Simon Hoerder; Marcin Wojcik; Stefan Tillich; Daniel Page

An evaluation of hash functions on a power analysis resistant processor architecture

Simon Hoerder, Marcin Wojcik, Stefan Tillich, Daniel Page

Cryptography and Information Security

Research output: Chapter in Book/Report/Conference proceeding › Conference Contribution (Conference Proceeding)

4 Citations (Scopus)

Abstract

Cryptographic hash functions are an omnipresent component in security-critical software and devices; they support digital signature and data authenticity schemes, mechanisms for key derivation, pseudo-random number generation and so on. A criterion for candidate hash functions in the SHA3 contest is resistance against side-channel analysis which is a major concern especially for mobile devices. This paper explores the implementation of said candidates on a variant of the Power-Trust platform; our results highlight a flexible solution to power analysis attacks, implying only a modest performance overhead.

Original language	English
Title of host publication	Workshop in Information Security Theory and Practice - WISTP 2011
Publisher	Springer Berlin Heidelberg
Pages	160-174
Volume	6633
Publication status	Published - 2011

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title = "An evaluation of hash functions on a power analysis resistant processor architecture",

abstract = "Cryptographic hash functions are an omnipresent component in security-critical software and devices; they support digital signature and data authenticity schemes, mechanisms for key derivation, pseudo-random number generation and so on. A criterion for candidate hash functions in the SHA3 contest is resistance against side-channel analysis which is a major concern especially for mobile devices. This paper explores the implementation of said candidates on a variant of the Power-Trust platform; our results highlight a flexible solution to power analysis attacks, implying only a modest performance overhead.",

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An evaluation of hash functions on a power analysis resistant processor architecture. / Hoerder, Simon; Wojcik, Marcin; Tillich, Stefan et al.
Workshop in Information Security Theory and Practice - WISTP 2011. Vol. 6633 Springer Berlin Heidelberg, 2011. p. 160-174.

Research output: Chapter in Book/Report/Conference proceeding › Conference Contribution (Conference Proceeding)

TY - GEN

T1 - An evaluation of hash functions on a power analysis resistant processor architecture

AU - Hoerder, Simon

AU - Wojcik, Marcin

AU - Tillich, Stefan

AU - Page, Daniel

PY - 2011

Y1 - 2011

N2 - Cryptographic hash functions are an omnipresent component in security-critical software and devices; they support digital signature and data authenticity schemes, mechanisms for key derivation, pseudo-random number generation and so on. A criterion for candidate hash functions in the SHA3 contest is resistance against side-channel analysis which is a major concern especially for mobile devices. This paper explores the implementation of said candidates on a variant of the Power-Trust platform; our results highlight a flexible solution to power analysis attacks, implying only a modest performance overhead.

AB - Cryptographic hash functions are an omnipresent component in security-critical software and devices; they support digital signature and data authenticity schemes, mechanisms for key derivation, pseudo-random number generation and so on. A criterion for candidate hash functions in the SHA3 contest is resistance against side-channel analysis which is a major concern especially for mobile devices. This paper explores the implementation of said candidates on a variant of the Power-Trust platform; our results highlight a flexible solution to power analysis attacks, implying only a modest performance overhead.

M3 - Conference Contribution (Conference Proceeding)

VL - 6633

SP - 160

EP - 174

BT - Workshop in Information Security Theory and Practice - WISTP 2011

PB - Springer Berlin Heidelberg

ER -

An evaluation of hash functions on a power analysis resistant processor architecture

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