Instruction Set Extensions (ISEs) supplement a host processor with special-purpose, typically fixed-function hardware components and instructions to utilize them. For cryptographic use-cases, this can be very effective due to the demand for non-standard or niche operations that are not supported by general-purpose architectures. However, one disadvantage of fixed-function ISEs is inflexibility, contradicting a need for “algorithm agility.” This paper explores a new approach, namely the provision of re-configurable mechanisms to support dynamic (run-time changeable) ISEs. Our results, obtained using an FPGA-based LEON3 prototype, show that this approach provides a flexible general-purpose platform for cryptographic ISEs with all known advantages of previous work, but relies on careful analysis of the associated security issues.
|Translated title of the contribution||An Exploration of Mechanisms for Dynamic Cryptographic Instruction Set Extension|
|Title of host publication||Cryptographic Hardware and Embedded Systems - CHES 2011|
|Publisher||Springer Berlin Heidelberg|
|Publication status||Published - 2011|
Grabher, P., Groszschaedl, J., Hoerder, S., Järvinen, K., Page, D., Tillich, S., & Wojcik, M. (2011). An exploration of mechanisms for dynamic cryptographic instruction set extension. In Cryptographic Hardware and Embedded Systems - CHES 2011 (Vol. 6917, pp. 1-16). Springer Berlin Heidelberg.