TY - GEN
T1 - An exploration of mechanisms for dynamic cryptographic instruction set extension
AU - Grabher, Philipp
AU - Groszschaedl, Johann
AU - Hoerder, Simon
AU - Järvinen, Kimmo
AU - Page, Daniel
AU - Tillich, Stefan
AU - Wojcik, Marcin
PY - 2011
Y1 - 2011
N2 - Instruction Set Extensions (ISEs) supplement a host processor with special-purpose, typically fixed-function hardware components and instructions to utilize them. For cryptographic use-cases, this can be very effective due to the demand for non-standard or niche operations that are not supported by general-purpose architectures. However, one disadvantage of fixed-function ISEs is inflexibility, contradicting a need for “algorithm agility.” This paper explores a new approach, namely the provision of re-configurable mechanisms to support dynamic (run-time changeable) ISEs. Our results, obtained using an FPGA-based LEON3 prototype, show that this approach provides a flexible general-purpose platform for cryptographic ISEs with all known advantages of previous work, but relies on careful analysis of the associated security issues.
AB - Instruction Set Extensions (ISEs) supplement a host processor with special-purpose, typically fixed-function hardware components and instructions to utilize them. For cryptographic use-cases, this can be very effective due to the demand for non-standard or niche operations that are not supported by general-purpose architectures. However, one disadvantage of fixed-function ISEs is inflexibility, contradicting a need for “algorithm agility.” This paper explores a new approach, namely the provision of re-configurable mechanisms to support dynamic (run-time changeable) ISEs. Our results, obtained using an FPGA-based LEON3 prototype, show that this approach provides a flexible general-purpose platform for cryptographic ISEs with all known advantages of previous work, but relies on careful analysis of the associated security issues.
M3 - Conference Contribution (Conference Proceeding)
VL - 6917
SP - 1
EP - 16
BT - Cryptographic Hardware and Embedded Systems - CHES 2011
PB - Springer Berlin Heidelberg
ER -