An exploration of mechanisms for dynamic cryptographic instruction set extension

Philipp Grabher; Johann Groszschaedl; Simon Hoerder; Kimmo Järvinen; Daniel Page; Stefan Tillich; Marcin Wojcik

An exploration of mechanisms for dynamic cryptographic instruction set extension

Philipp Grabher, Johann Groszschaedl, Simon Hoerder, Kimmo Järvinen, Daniel Page, Stefan Tillich, Marcin Wojcik

Research output: Chapter in Book/Report/Conference proceeding › Conference Contribution (Conference Proceeding)

1 Citation (Scopus)

Abstract

Instruction Set Extensions (ISEs) supplement a host processor with special-purpose, typically fixed-function hardware components and instructions to utilize them. For cryptographic use-cases, this can be very effective due to the demand for non-standard or niche operations that are not supported by general-purpose architectures. However, one disadvantage of fixed-function ISEs is inflexibility, contradicting a need for “algorithm agility.” This paper explores a new approach, namely the provision of re-configurable mechanisms to support dynamic (run-time changeable) ISEs. Our results, obtained using an FPGA-based LEON3 prototype, show that this approach provides a flexible general-purpose platform for cryptographic ISEs with all known advantages of previous work, but relies on careful analysis of the associated security issues.

Translated title of the contribution	An Exploration of Mechanisms for Dynamic Cryptographic Instruction Set Extension
Original language	English
Title of host publication	Cryptographic Hardware and Embedded Systems - CHES 2011
Publisher	Springer Berlin Heidelberg
Pages	1-16
Volume	6917
Publication status	Published - 2011

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Grabher, P., Groszschaedl, J., Hoerder, S., Järvinen, K., Page, D., Tillich, S., & Wojcik, M. (2011). An exploration of mechanisms for dynamic cryptographic instruction set extension. In Cryptographic Hardware and Embedded Systems - CHES 2011 (Vol. 6917, pp. 1-16). Springer Berlin Heidelberg.

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title = "An exploration of mechanisms for dynamic cryptographic instruction set extension",

abstract = "Instruction Set Extensions (ISEs) supplement a host processor with special-purpose, typically fixed-function hardware components and instructions to utilize them. For cryptographic use-cases, this can be very effective due to the demand for non-standard or niche operations that are not supported by general-purpose architectures. However, one disadvantage of fixed-function ISEs is inflexibility, contradicting a need for “algorithm agility.” This paper explores a new approach, namely the provision of re-configurable mechanisms to support dynamic (run-time changeable) ISEs. Our results, obtained using an FPGA-based LEON3 prototype, show that this approach provides a flexible general-purpose platform for cryptographic ISEs with all known advantages of previous work, but relies on careful analysis of the associated security issues.",

author = "Philipp Grabher and Johann Groszschaedl and Simon Hoerder and Kimmo J{\"a}rvinen and Daniel Page and Stefan Tillich and Marcin Wojcik",

year = "2011",

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An exploration of mechanisms for dynamic cryptographic instruction set extension. / Grabher, Philipp; Groszschaedl, Johann; Hoerder, Simon; Järvinen, Kimmo; Page, Daniel; Tillich, Stefan; Wojcik, Marcin.

Cryptographic Hardware and Embedded Systems - CHES 2011. Vol. 6917 Springer Berlin Heidelberg, 2011. p. 1-16.

Research output: Chapter in Book/Report/Conference proceeding › Conference Contribution (Conference Proceeding)

TY - GEN

T1 - An exploration of mechanisms for dynamic cryptographic instruction set extension

AU - Grabher, Philipp

AU - Groszschaedl, Johann

AU - Hoerder, Simon

AU - Järvinen, Kimmo

AU - Page, Daniel

AU - Tillich, Stefan

AU - Wojcik, Marcin

PY - 2011

Y1 - 2011

N2 - Instruction Set Extensions (ISEs) supplement a host processor with special-purpose, typically fixed-function hardware components and instructions to utilize them. For cryptographic use-cases, this can be very effective due to the demand for non-standard or niche operations that are not supported by general-purpose architectures. However, one disadvantage of fixed-function ISEs is inflexibility, contradicting a need for “algorithm agility.” This paper explores a new approach, namely the provision of re-configurable mechanisms to support dynamic (run-time changeable) ISEs. Our results, obtained using an FPGA-based LEON3 prototype, show that this approach provides a flexible general-purpose platform for cryptographic ISEs with all known advantages of previous work, but relies on careful analysis of the associated security issues.

AB - Instruction Set Extensions (ISEs) supplement a host processor with special-purpose, typically fixed-function hardware components and instructions to utilize them. For cryptographic use-cases, this can be very effective due to the demand for non-standard or niche operations that are not supported by general-purpose architectures. However, one disadvantage of fixed-function ISEs is inflexibility, contradicting a need for “algorithm agility.” This paper explores a new approach, namely the provision of re-configurable mechanisms to support dynamic (run-time changeable) ISEs. Our results, obtained using an FPGA-based LEON3 prototype, show that this approach provides a flexible general-purpose platform for cryptographic ISEs with all known advantages of previous work, but relies on careful analysis of the associated security issues.

M3 - Conference Contribution (Conference Proceeding)

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BT - Cryptographic Hardware and Embedded Systems - CHES 2011

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