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An exploration of mechanisms for dynamic cryptographic instruction set extension

Research output: Chapter in Book/Report/Conference proceedingConference contribution

  • Philipp Grabher
  • Johann Groszschaedl
  • Simon Hoerder
  • Kimmo Järvinen
  • Daniel Page
  • Stefan Tillich
  • Marcin Wojcik
Original languageEnglish
Title of host publicationCryptographic Hardware and Embedded Systems - CHES 2011
Publisher or commissioning bodySpringer Berlin Heidelberg
DatePublished - 2011


Instruction Set Extensions (ISEs) supplement a host processor with special-purpose, typically fixed-function hardware components and instructions to utilize them. For cryptographic use-cases, this can be very effective due to the demand for non-standard or niche operations that are not supported by general-purpose architectures. However, one disadvantage of fixed-function ISEs is inflexibility, contradicting a need for “algorithm agility.” This paper explores a new approach, namely the provision of re-configurable mechanisms to support dynamic (run-time changeable) ISEs. Our results, obtained using an FPGA-based LEON3 prototype, show that this approach provides a flexible general-purpose platform for cryptographic ISEs with all known advantages of previous work, but relies on careful analysis of the associated security issues.


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