An improved architecture for the adaptive discrete cosine transform

F Martin; DR Bull

doi:10.1109/ISCAS.1996.541832

An improved architecture for the adaptive discrete cosine transform

F Martin, DR Bull

Department of Electrical & Electronic Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference Contribution (Conference Proceeding)

2 Citations (Scopus)

325 Downloads (Pure)

Abstract

This paper presents a new approach to the efficient realisation of the discrete cosine transform for the specific case of interlaced image sequence coding. In such cases, the conventional approach of decomposing each frame or frame difference into 8×8 blocks is often no longer satisfactory and an adaptive architecture capable of processing either 8×8 or two 4×8 blocks is desirable. The approach described is based on the decomposition used by Madisetti, modified to maximise shared hardware resources and to exploit arithmetic redundancy using primitive operator methods. The resulting architecture is compared with alternative implementation options using an area-time metric with savings in excess of 50% having been observed.

Translated title of the contribution	An Improved architecture for the adaptive discrete cosine transform
Original language	English
Title of host publication	Unknown
Publisher	Institute of Electrical and Electronics Engineers (IEEE)
Pages	742 - 745
Volume	2
ISBN (Print)	078030730, 0780330730
DOIs	https://doi.org/10.1109/ISCAS.1996.541832
Publication status	Published - May 1996
Event	IEEE International Symposium on Circuits and Systems, 1996 - Atlanta, United States Duration: 1 May 1996 → …

Conference

Conference	IEEE International Symposium on Circuits and Systems, 1996
Abbreviated title	ISCAS '96
Country/Territory	United States
City	Atlanta
Period	1/05/96 → …

Bibliographical note

Conference Proceedings/Title of Journal: IEEE intl. symp. on circuits and systems
Rose publication type: Conference contribution

Sponsorship: The authors wish to thank Sony Broadcast and Professional Europe and the Centre for Communications Research at Bristol University for their support of this work.

Terms of use: Copyright © 1996 IEEE. Reprinted from IEEE International Symposium on Circuits and Systems, 1996 (ISCAS '96).

This material is posted here with permission of the IEEE. Such permission of the IEEE does not in any way imply IEEE endorsement of any of the University of Bristol's products or services. Internal or personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution must be obtained from the IEEE by writing to [email protected].

By choosing to view this document, you agree to all provisions of the copyright laws protecting it.

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10.1109/ISCAS.1996.541832

Martin IEEE ISCAS 1996Accepted author manuscript, 379 KB

http://hdl.handle.net/1983/1345

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Cite this

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title = "An improved architecture for the adaptive discrete cosine transform",

abstract = "This paper presents a new approach to the efficient realisation of the discrete cosine transform for the specific case of interlaced image sequence coding. In such cases, the conventional approach of decomposing each frame or frame difference into 8×8 blocks is often no longer satisfactory and an adaptive architecture capable of processing either 8×8 or two 4×8 blocks is desirable. The approach described is based on the decomposition used by Madisetti, modified to maximise shared hardware resources and to exploit arithmetic redundancy using primitive operator methods. The resulting architecture is compared with alternative implementation options using an area-time metric with savings in excess of 50% having been observed.",

author = "F Martin and DR Bull",

note = "Conference Proceedings/Title of Journal: IEEE intl. symp. on circuits and systems Rose publication type: Conference contribution Sponsorship: The authors wish to thank Sony Broadcast and Professional Europe and the Centre for Communications Research at Bristol University for their support of this work. Terms of use: Copyright {\textcopyright} 1996 IEEE. Reprinted from IEEE International Symposium on Circuits and Systems, 1996 (ISCAS '96). This material is posted here with permission of the IEEE. Such permission of the IEEE does not in any way imply IEEE endorsement of any of the University of Bristol's products or services. Internal or personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution must be obtained from the IEEE by writing to [email protected]. By choosing to view this document, you agree to all provisions of the copyright laws protecting it. ; IEEE International Symposium on Circuits and Systems, 1996, ISCAS '96 ; Conference date: 01-05-1996",

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doi = "10.1109/ISCAS.1996.541832",

language = "English",

isbn = "078030730",

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AU - Bull, DR

N1 - Conference Proceedings/Title of Journal: IEEE intl. symp. on circuits and systems Rose publication type: Conference contribution Sponsorship: The authors wish to thank Sony Broadcast and Professional Europe and the Centre for Communications Research at Bristol University for their support of this work. Terms of use: Copyright © 1996 IEEE. Reprinted from IEEE International Symposium on Circuits and Systems, 1996 (ISCAS '96). This material is posted here with permission of the IEEE. Such permission of the IEEE does not in any way imply IEEE endorsement of any of the University of Bristol's products or services. Internal or personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution must be obtained from the IEEE by writing to [email protected]. By choosing to view this document, you agree to all provisions of the copyright laws protecting it.

PY - 1996/5

Y1 - 1996/5

N2 - This paper presents a new approach to the efficient realisation of the discrete cosine transform for the specific case of interlaced image sequence coding. In such cases, the conventional approach of decomposing each frame or frame difference into 8×8 blocks is often no longer satisfactory and an adaptive architecture capable of processing either 8×8 or two 4×8 blocks is desirable. The approach described is based on the decomposition used by Madisetti, modified to maximise shared hardware resources and to exploit arithmetic redundancy using primitive operator methods. The resulting architecture is compared with alternative implementation options using an area-time metric with savings in excess of 50% having been observed.

AB - This paper presents a new approach to the efficient realisation of the discrete cosine transform for the specific case of interlaced image sequence coding. In such cases, the conventional approach of decomposing each frame or frame difference into 8×8 blocks is often no longer satisfactory and an adaptive architecture capable of processing either 8×8 or two 4×8 blocks is desirable. The approach described is based on the decomposition used by Madisetti, modified to maximise shared hardware resources and to exploit arithmetic redundancy using primitive operator methods. The resulting architecture is compared with alternative implementation options using an area-time metric with savings in excess of 50% having been observed.

U2 - 10.1109/ISCAS.1996.541832

DO - 10.1109/ISCAS.1996.541832

M3 - Conference Contribution (Conference Proceeding)

SN - 078030730

SN - 0780330730

VL - 2

SP - 742

EP - 745

BT - Unknown

PB - Institute of Electrical and Electronics Engineers (IEEE)

T2 - IEEE International Symposium on Circuits and Systems, 1996

Y2 - 1 May 1996

ER -

An improved architecture for the adaptive discrete cosine transform

Abstract

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