This paper presents an ultra low-power class AB operational amplifier (OpAmp) designed in a low-cost 0.18 μm CMOS technology. Rail-to-rail input operation is achieved by using complementary input pairs with adaptive bias to enhance slew-rate. A class AB output stage is employed. For low-voltage low-power operation, the transistors both in the input and the output stage are biased in the sub-threshold region. The simulated DC open loop gain is 51 dB, the unity gain frequency is 40 kHz with a 65°phase margin and the slew-rate is 0.12 V/μs with 10 pF capacitive loads. A common-mode feed-forward circuit (CMFF) increases CMRR, keeping the DC gain almost constant: its relative error remains below 1 % for a (40°C, +120°C) temperature range. The proposed OpAmp consumes only 1 μW at 0.8 V supply.
|Number of pages||4|
|Publication status||Published - 28 Sep 2012|
|Event||2012 IEEE International Symposium on Circuits and Systems, ISCAS 2012 - Seoul, Korea, Republic of|
Duration: 20 May 2012 → 23 May 2012
|Conference||2012 IEEE International Symposium on Circuits and Systems, ISCAS 2012|
|Country||Korea, Republic of|
|Period||20/05/12 → 23/05/12|