An ultra low-power low-voltage class AB CMOS fully differential OpAmp

M. R. Valero; Santiago Celma-Pueyo; N. Medrano; B. Calvo; C. Azcona

doi:10.1109/ISCAS.2012.6271661

An ultra low-power low-voltage class AB CMOS fully differential OpAmp

M. R. Valero^*, Santiago Celma-Pueyo, N. Medrano, B. Calvo, C. Azcona

^*Corresponding author for this work

Research output: Contribution to conference › Conference Paper › peer-review

15 Citations (Scopus)

Abstract

This paper presents an ultra low-power class AB operational amplifier (OpAmp) designed in a low-cost 0.18 μm CMOS technology. Rail-to-rail input operation is achieved by using complementary input pairs with adaptive bias to enhance slew-rate. A class AB output stage is employed. For low-voltage low-power operation, the transistors both in the input and the output stage are biased in the sub-threshold region. The simulated DC open loop gain is 51 dB, the unity gain frequency is 40 kHz with a 65°phase margin and the slew-rate is 0.12 V/μs with 10 pF capacitive loads. A common-mode feed-forward circuit (CMFF) increases CMRR, keeping the DC gain almost constant: its relative error remains below 1 % for a (40°C, +120°C) temperature range. The proposed OpAmp consumes only 1 μW at 0.8 V supply.

Original language	English
Pages	1967-1970
Number of pages	4
DOIs	https://doi.org/10.1109/ISCAS.2012.6271661
Publication status	Published - 28 Sep 2012
Event	2012 IEEE International Symposium on Circuits and Systems, ISCAS 2012 - Seoul, Korea, Republic of Duration: 20 May 2012 → 23 May 2012

Conference

Conference	2012 IEEE International Symposium on Circuits and Systems, ISCAS 2012
Country/Territory	Korea, Republic of
City	Seoul
Period	20/05/12 → 23/05/12

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10.1109/ISCAS.2012.6271661

Cite this

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title = "An ultra low-power low-voltage class AB CMOS fully differential OpAmp",

abstract = "This paper presents an ultra low-power class AB operational amplifier (OpAmp) designed in a low-cost 0.18 μm CMOS technology. Rail-to-rail input operation is achieved by using complementary input pairs with adaptive bias to enhance slew-rate. A class AB output stage is employed. For low-voltage low-power operation, the transistors both in the input and the output stage are biased in the sub-threshold region. The simulated DC open loop gain is 51 dB, the unity gain frequency is 40 kHz with a 65°phase margin and the slew-rate is 0.12 V/μs with 10 pF capacitive loads. A common-mode feed-forward circuit (CMFF) increases CMRR, keeping the DC gain almost constant: its relative error remains below 1 % for a (40°C, +120°C) temperature range. The proposed OpAmp consumes only 1 μW at 0.8 V supply.",

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AU - Valero, M. R.

AU - Celma-Pueyo, Santiago

AU - Medrano, N.

AU - Calvo, B.

AU - Azcona, C.

PY - 2012/9/28

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N2 - This paper presents an ultra low-power class AB operational amplifier (OpAmp) designed in a low-cost 0.18 μm CMOS technology. Rail-to-rail input operation is achieved by using complementary input pairs with adaptive bias to enhance slew-rate. A class AB output stage is employed. For low-voltage low-power operation, the transistors both in the input and the output stage are biased in the sub-threshold region. The simulated DC open loop gain is 51 dB, the unity gain frequency is 40 kHz with a 65°phase margin and the slew-rate is 0.12 V/μs with 10 pF capacitive loads. A common-mode feed-forward circuit (CMFF) increases CMRR, keeping the DC gain almost constant: its relative error remains below 1 % for a (40°C, +120°C) temperature range. The proposed OpAmp consumes only 1 μW at 0.8 V supply.

AB - This paper presents an ultra low-power class AB operational amplifier (OpAmp) designed in a low-cost 0.18 μm CMOS technology. Rail-to-rail input operation is achieved by using complementary input pairs with adaptive bias to enhance slew-rate. A class AB output stage is employed. For low-voltage low-power operation, the transistors both in the input and the output stage are biased in the sub-threshold region. The simulated DC open loop gain is 51 dB, the unity gain frequency is 40 kHz with a 65°phase margin and the slew-rate is 0.12 V/μs with 10 pF capacitive loads. A common-mode feed-forward circuit (CMFF) increases CMRR, keeping the DC gain almost constant: its relative error remains below 1 % for a (40°C, +120°C) temperature range. The proposed OpAmp consumes only 1 μW at 0.8 V supply.

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T2 - 2012 IEEE International Symposium on Circuits and Systems, ISCAS 2012

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An ultra low-power low-voltage class AB CMOS fully differential OpAmp

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