Area, Delay, and Power Characteristics of Standard-Cell Implementations of the AES S-Box

Stefan Tillich, Martin Feldhofer, Thomas Popp, Johann Großschädl

Research output: Contribution to journalArticle (Academic Journal)peer-review

26 Citations (Scopus)

Abstract

Cryptographic substitution boxes (S-boxes) are an integral part of modern block ciphers like the Advanced Encryption Standard (AES). There exists a rich literature devoted to the efficient implementation of cryptographic S-boxes, wherein hardware designs for FPGAs and standard cells received particular attention. In this paper we present a comprehensive study of different standard-cell implementations of the AES S-box with respect to timing (i.e. critical path), silicon area, power consumption, and combinations of these cost metrics. We examine implementations which exploit the mathematical properties of the AES S-box, constructions based on hardware look-up tables, and dedicated low-power solutions. Our results show that the timing, area, and power properties of the different S-box realizations can vary by up to almost an order of magnitude. In terms of area and area-delay product, the best choice are implementations which calculate the S-box output. On the other hand, the hardware look-up solutions are characterized by the shortest critical path. The dedicated low-power implementations do not only reduce power consumption by a large degree, but they also show good timing properties and offer the best power-delay and power-area product, respectively.
Translated title of the contributionArea, Delay, and Power Characteristics of Standard-Cell Implementations of the AES S-Box
Original languageEnglish
Pages (from-to)251-261
JournalJournal of Signal Processing Systems
Volume50(2)
Publication statusPublished - 2008

Bibliographical note

Other identifier: 2000920

Fingerprint

Dive into the research topics of 'Area, Delay, and Power Characteristics of Standard-Cell Implementations of the AES S-Box'. Together they form a unique fingerprint.

Cite this