Assessment of Butterfly Network VLSI Shifter Circuit

N Burgess

Research output: Chapter in Book/Report/Conference proceedingConference Contribution (Conference Proceeding)

1 Citation (Scopus)


Recently, a new proposal for implementing shifters in VLSI using a butterfly network has been published. This paper assesses the claims made for this shifter when compared with a conventional shifter constructed as a number of rows of multiplexers each with a common control signal. Comparisons of area and delay are made both by using the Logical Effort delay model and by simulation of a manully placed implementation in a 65nm CMOS VLSI design flow.
Translated title of the contributionAssessment of Butterfly Network VLSI Shifter Circuit
Original languageEnglish
Title of host publicationProc. 44th IEEE Asilomar Conference on Signals, Systems and Computers
Publication statusPublished - 2010

Bibliographical note

Name and Venue of Event: Asilomar, CA
Conference Organiser: IEEE

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