Recently, a new proposal for implementing shifters in VLSI using a butterfly network has been published. This paper assesses the claims made for this shifter when compared with a conventional shifter constructed as a number of rows of multiplexers each with a common control signal. Comparisons of area and delay are made both by using the Logical Effort delay model and by simulation of a manully placed implementation in a 65nm CMOS VLSI design flow.
|Translated title of the contribution||Assessment of Butterfly Network VLSI Shifter Circuit|
|Title of host publication||Proc. 44th IEEE Asilomar Conference on Signals, Systems and Computers|
|Publication status||Published - 2010|
Bibliographical noteName and Venue of Event: Asilomar, CA
Conference Organiser: IEEE