Assessment of Butterfly Network VLSI Shifter Circuit

N Burgess

Assessment of Butterfly Network VLSI Shifter Circuit

N Burgess

Research output: Chapter in Book/Report/Conference proceeding › Conference Contribution (Conference Proceeding)

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Abstract

Recently, a new proposal for implementing shifters in VLSI using a butterfly network has been published. This paper assesses the claims made for this shifter when compared with a conventional shifter constructed as a number of rows of multiplexers each with a common control signal. Comparisons of area and delay are made both by using the Logical Effort delay model and by simulation of a manully placed implementation in a 65nm CMOS VLSI design flow.

Translated title of the contribution	Assessment of Butterfly Network VLSI Shifter Circuit
Original language	English
Title of host publication	Proc. 44th IEEE Asilomar Conference on Signals, Systems and Computers
Publication status	Published - 2010

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Name and Venue of Event: Asilomar, CA
Conference Organiser: IEEE

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@inproceedings{c6bc66895d6b4af1a9cbc0131d29f8a4,

title = "Assessment of Butterfly Network VLSI Shifter Circuit",

abstract = "Recently, a new proposal for implementing shifters in VLSI using a butterfly network has been published. This paper assesses the claims made for this shifter when compared with a conventional shifter constructed as a number of rows of multiplexers each with a common control signal. Comparisons of area and delay are made both by using the Logical Effort delay model and by simulation of a manully placed implementation in a 65nm CMOS VLSI design flow.",

author = "N Burgess",

note = "Name and Venue of Event: Asilomar, CA Conference Organiser: IEEE",

year = "2010",

language = "English",

booktitle = "Proc. 44th IEEE Asilomar Conference on Signals, Systems and Computers",

}

TY - GEN

T1 - Assessment of Butterfly Network VLSI Shifter Circuit

AU - Burgess, N

N1 - Name and Venue of Event: Asilomar, CA Conference Organiser: IEEE

PY - 2010

Y1 - 2010

N2 - Recently, a new proposal for implementing shifters in VLSI using a butterfly network has been published. This paper assesses the claims made for this shifter when compared with a conventional shifter constructed as a number of rows of multiplexers each with a common control signal. Comparisons of area and delay are made both by using the Logical Effort delay model and by simulation of a manully placed implementation in a 65nm CMOS VLSI design flow.

AB - Recently, a new proposal for implementing shifters in VLSI using a butterfly network has been published. This paper assesses the claims made for this shifter when compared with a conventional shifter constructed as a number of rows of multiplexers each with a common control signal. Comparisons of area and delay are made both by using the Logical Effort delay model and by simulation of a manully placed implementation in a 65nm CMOS VLSI design flow.

M3 - Conference Contribution (Conference Proceeding)

BT - Proc. 44th IEEE Asilomar Conference on Signals, Systems and Computers

ER -

Assessment of Butterfly Network VLSI Shifter Circuit

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