Bandwidth Optimization for Through-Silicon Via (TSV) Bundles in 3-D Integrated Circuits

A Weldezion, Roshan Weerasekera, Dinesh Pamunuwa, Li-Rong Zheng, Hannu Tenhunen

Research output: Chapter in Book/Report/Conference proceedingConference Contribution (Conference Proceeding)

Original languageUndefined/Unknown
Title of host publicationProc. Special Interest Workshop on 3D Integration -- Design Automation and Test in Europe (DATE)
Publication statusPublished - 1 Apr 2009

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