Bandwidth Optimization for Through-Silicon Via (TSV) Bundles in 3-D Integrated Circuits

A Weldezion, Roshan Weerasekera, Dinesh Pamunuwa, Li-Rong Zheng, Hannu Tenhunen

Research output: Chapter in Book/Report/Conference proceeding › Conference Contribution (Conference Proceeding)

Original language	Undefined/Unknown
Title of host publication	Proc. Special Interest Workshop on 3D Integration -- Design Automation and Test in Europe (DATE)
Publication status	Published - 1 Apr 2009

Research Groups and Themes

@inproceedings{bfff2adfe77244d38668906067d585d7,

title = "Bandwidth Optimization for Through-Silicon Via (TSV) Bundles in 3-D Integrated Circuits",

author = "A Weldezion and Roshan Weerasekera and Dinesh Pamunuwa and Li-Rong Zheng and Hannu Tenhunen",

year = "2009",

month = apr,

day = "1",

language = "Undefined/Unknown",

booktitle = "Proc. Special Interest Workshop on 3D Integration -- Design Automation and Test in Europe (DATE)",

}

TY - GEN

T1 - Bandwidth Optimization for Through-Silicon Via (TSV) Bundles in 3-D Integrated Circuits

AU - Weldezion, A

AU - Weerasekera, Roshan

AU - Pamunuwa, Dinesh

AU - Zheng, Li-Rong

AU - Tenhunen, Hannu

PY - 2009/4/1

Y1 - 2009/4/1

M3 - Conference Contribution (Conference Proceeding)

BT - Proc. Special Interest Workshop on 3D Integration -- Design Automation and Test in Europe (DATE)

ER -