C-Testable Bit Parallel Multipliers Over GF(2m)

H. Rahaman, Jimson Mathew, Pradhan Dhiraj, A.M. Jamir

Research output: Contribution to journalArticle (Academic Journal)peer-review

7 Citations (Scopus)


We present a C-testable design of polynomial basis (PB) bit-parallel (BP) multipliers over GF(2m)
for 100% coverage of stuck-at faults. Our design method also includes the method for test vector
generation, which is simple and efficient. C-testability is achieved with three control inputs and
approximately 6% additional hardware. Only 8 constant vectors are required irrespective of the
sizes of the fields and primitive polynomial. We also present a Built-In Self-Test (BIST) architecture
for generating the test vectors efficiently, which eliminates the need for the extra control inputs.
Since these circuits have critical applications as parts of cryptography (e.g., Elliptic Curve Crypto
(ECC) systems) hardware, the BIST architecture may provide with added level of security, as
the tests would be done internally and without the requirement of probing by external testing
equipment. Finally we present experimental results comprising the area, delay and power of the
testable multipliers of various sizes with the help of the Synopsys tools using UMC 0.18 micron
CMOS technology library.
Translated title of the contributionC-Testable Bit Parallel Multipliers Over GF(2m)
Original languageEnglish
Article number-
Pages (from-to)5-13
JournalTransactions on Design Automation of Electronic Systems
Issue number1
Publication statusPublished - 2008

Bibliographical note

Other identifier: 2000726


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