CAD-Directed SEU Susceptibility Reduction in FPGA Circuits Designs

Zarandi H, S.G. Miremadi, Pradhan Dhiraj, Jimson Mathew

Research output: Chapter in Book/Report/Conference proceedingConference Contribution (Conference Proceeding)

1 Citation (Scopus)
Translated title of the contributionCAD-Directed SEU Susceptibility Reduction in FPGA Circuits Designs
Original languageEnglish
Title of host publicationIEEE International Conference on Circuits and Systems, (ISCAS 2007), USA
PublisherInstitute of Electrical and Electronics Engineers (IEEE)
Publication statusPublished - 2007

Bibliographical note

Other page information: -
Conference Proceedings/Title of Journal: IEEE International Conference on Circuits and Systems, (ISCAS 2007), USA
Other identifier: 2000665

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