Can DSP48A1 adders be used for high-resolution delay generation?

Scott Tancock; Ekin Arabul; Naim Dahnoun; Shahid Mehmood

doi:10.1109/MECO.2018.8406083

Can DSP48A1 adders be used for high-resolution delay generation?

Scott Tancock, Ekin Arabul, Naim Dahnoun, Shahid Mehmood

Research output: Chapter in Book/Report/Conference proceeding › Conference Contribution (Conference Proceeding)

10 Citations (Scopus)

402 Downloads (Pure)

Abstract

Time to digital conversion is an important task in many systems. It involves the conversion of time-based signals (as opposed to the amplitude-based signals in analog-to-digital conversion) into digital numbers so that a purely digital system may process them. This is widely used in rangefinders, all-digital phase-locked loops and quantum experiments. In order to obtain high-resolution time-to-digital conversion, the generation of small delays is necessary. This paper examines the viability of using the DSP48A1 blocks present on Xilinx FPGAs to generate these small delays, and ultimately concludes they are unsuitable in isolation due to the high differential non-linearity, but may be suitable as a semi-fine stage of a multi-stage TDC or when combined in an equivalent coding line.

Original language	English
Title of host publication	2018 7th Mediterranean Conference on Embedded Computing (MECO 2018)
Subtitle of host publication	Proceedings of a meeting held 10-14 June 2018, Budva, Montenegro
Editors	Lech Jozwiak, Budimir Lutovac, Drazen Jurisic, Radovan Stojanovic
Publisher	Institute of Electrical and Electronics Engineers (IEEE)
Pages	370-375
Number of pages	6
ISBN (Electronic)	9781538656822
ISBN (Print)	9781538656846
DOIs	https://doi.org/10.1109/MECO.2018.8406083
Publication status	Published - Aug 2018
Event	7th Mediterranean Conference on Embedded Computing, MECO 2018: MECO 2018 - Budva, Montenegro Duration: 10 Jun 2018 → 14 Jun 2018

Publication series

Name
ISSN (Print)	2377-5475

Conference

Conference	7th Mediterranean Conference on Embedded Computing, MECO 2018
Country/Territory	Montenegro
City	Budva
Period	10/06/18 → 14/06/18

Keywords

Delay Generation
Digital Signal Processing
Field-Programmable Gate Arrays
Time-to-Digital Converters
Xilinx

Access to Document

10.1109/MECO.2018.8406083

Full-text PDF (accepted author manuscript)
This is the author accepted manuscript (AAM). The final published version (version of record) is available online via IEEE at https://ieeexplore.ieee.org/document/8406083 . Please refer to any applicable terms of use of the publisher.
Accepted author manuscript, 401 KB

Handle.net

Persistent link

Cite this

Tancock, S., Arabul, E., Dahnoun, N., & Mehmood, S. (2018). Can DSP48A1 adders be used for high-resolution delay generation? In L. Jozwiak, B. Lutovac, D. Jurisic, & R. Stojanovic (Eds.), 2018 7th Mediterranean Conference on Embedded Computing (MECO 2018): Proceedings of a meeting held 10-14 June 2018, Budva, Montenegro (pp. 370-375). Institute of Electrical and Electronics Engineers (IEEE). https://doi.org/10.1109/MECO.2018.8406083

Tancock, Scott ; Arabul, Ekin ; Dahnoun, Naim et al. / Can DSP48A1 adders be used for high-resolution delay generation?. 2018 7th Mediterranean Conference on Embedded Computing (MECO 2018): Proceedings of a meeting held 10-14 June 2018, Budva, Montenegro. editor / Lech Jozwiak ; Budimir Lutovac ; Drazen Jurisic ; Radovan Stojanovic. Institute of Electrical and Electronics Engineers (IEEE), 2018. pp. 370-375

@inproceedings{a8490a3fb47c437f9ed48be3f8ec9135,

title = "Can DSP48A1 adders be used for high-resolution delay generation?",

abstract = "Time to digital conversion is an important task in many systems. It involves the conversion of time-based signals (as opposed to the amplitude-based signals in analog-to-digital conversion) into digital numbers so that a purely digital system may process them. This is widely used in rangefinders, all-digital phase-locked loops and quantum experiments. In order to obtain high-resolution time-to-digital conversion, the generation of small delays is necessary. This paper examines the viability of using the DSP48A1 blocks present on Xilinx FPGAs to generate these small delays, and ultimately concludes they are unsuitable in isolation due to the high differential non-linearity, but may be suitable as a semi-fine stage of a multi-stage TDC or when combined in an equivalent coding line.",

keywords = "Delay Generation, Digital Signal Processing, Field-Programmable Gate Arrays, Time-to-Digital Converters, Xilinx",

author = "Scott Tancock and Ekin Arabul and Naim Dahnoun and Shahid Mehmood",

year = "2018",

month = aug,

doi = "10.1109/MECO.2018.8406083",

language = "English",

isbn = "9781538656846",

publisher = "Institute of Electrical and Electronics Engineers (IEEE)",

pages = "370--375",

editor = "Lech Jozwiak and Budimir Lutovac and Drazen Jurisic and Radovan Stojanovic",

booktitle = "2018 7th Mediterranean Conference on Embedded Computing (MECO 2018)",

address = "United States",

note = "7th Mediterranean Conference on Embedded Computing, MECO 2018 : MECO 2018 ; Conference date: 10-06-2018 Through 14-06-2018",

}

Tancock, S, Arabul, E , Dahnoun, N & Mehmood, S 2018, Can DSP48A1 adders be used for high-resolution delay generation? in L Jozwiak, B Lutovac, D Jurisic & R Stojanovic (eds), 2018 7th Mediterranean Conference on Embedded Computing (MECO 2018): Proceedings of a meeting held 10-14 June 2018, Budva, Montenegro. Institute of Electrical and Electronics Engineers (IEEE), pp. 370-375, 7th Mediterranean Conference on Embedded Computing, MECO 2018, Budva, Montenegro, 10/06/18. https://doi.org/10.1109/MECO.2018.8406083

Can DSP48A1 adders be used for high-resolution delay generation? / Tancock, Scott; Arabul, Ekin ; Dahnoun, Naim et al.
2018 7th Mediterranean Conference on Embedded Computing (MECO 2018): Proceedings of a meeting held 10-14 June 2018, Budva, Montenegro. ed. / Lech Jozwiak; Budimir Lutovac; Drazen Jurisic; Radovan Stojanovic. Institute of Electrical and Electronics Engineers (IEEE), 2018. p. 370-375.

Research output: Chapter in Book/Report/Conference proceeding › Conference Contribution (Conference Proceeding)