Can DSP48A1 adders be used for high-resolution delay generation?

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Abstract

Time to digital conversion is an important task in many systems. It involves the conversion of time-based signals (as opposed to the amplitude-based signals in analog-to-digital conversion) into digital numbers so that a purely digital system may process them. This is widely used in rangefinders, all-digital phase-locked loops and quantum experiments. In order to obtain high-resolution time-to-digital conversion, the generation of small delays is necessary. This paper examines the viability of using the DSP48A1 blocks present on Xilinx FPGAs to generate these small delays, and ultimately concludes they are unsuitable in isolation due to the high differential non-linearity, but may be suitable as a semi-fine stage of a multi-stage TDC or when combined in an equivalent coding line.

Original languageEnglish
Title of host publication2018 7th Mediterranean Conference on Embedded Computing (MECO 2018)
Subtitle of host publicationProceedings of a meeting held 10-14 June 2018, Budva, Montenegro
EditorsLech Jozwiak, Budimir Lutovac, Drazen Jurisic, Radovan Stojanovic
PublisherInstitute of Electrical and Electronics Engineers (IEEE)
Pages370-375
Number of pages6
ISBN (Electronic)9781538656822
ISBN (Print)9781538656846
DOIs
Publication statusPublished - Aug 2018
Event7th Mediterranean Conference on Embedded Computing, MECO 2018: MECO 2018 - Budva, Montenegro
Duration: 10 Jun 201814 Jun 2018

Publication series

Name
ISSN (Print)2377-5475

Conference

Conference7th Mediterranean Conference on Embedded Computing, MECO 2018
CountryMontenegro
CityBudva
Period10/06/1814/06/18

Keywords

  • Delay Generation
  • Digital Signal Processing
  • Field-Programmable Gate Arrays
  • Time-to-Digital Converters
  • Xilinx

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