TY - GEN
T1 - Class AB two stage and folded cascode OpAmps based on a squaring circuit
AU - Valero, M. R.
AU - Lopez-Martin, Antonio
AU - Thoutam, Shanta
AU - Ramirez-Angulo, Jaime
AU - Carvajal, Ramon G.
PY - 2015/7/27
Y1 - 2015/7/27
N2 - This paper presents a novel adaptive bias technique based on the use of squaring circuits. Here, the tail current of an operational amplifier (OpAmp) is controlled using an auxiliary circuit. By design, it generates a well-controlled tail current which - to a first order approximation - is independent of the OpAmp's common-mode input voltage. As a result, parameters like common-mode rejection ratio (CMRR) and power supply rejection ratio (PSRR) are enhanced. However, when a differential input signal is applied, it generates a tail current proportional to the square of the OpAmp's differential input voltage. In this way, the currents of the OpAmp's input pairs are boosted, thus improving slew rate. Experimental results in 0.5 μm CMOS technology verify current and slew rate enhancement factors between 10 and 15 with less than 20% static current increase.
AB - This paper presents a novel adaptive bias technique based on the use of squaring circuits. Here, the tail current of an operational amplifier (OpAmp) is controlled using an auxiliary circuit. By design, it generates a well-controlled tail current which - to a first order approximation - is independent of the OpAmp's common-mode input voltage. As a result, parameters like common-mode rejection ratio (CMRR) and power supply rejection ratio (PSRR) are enhanced. However, when a differential input signal is applied, it generates a tail current proportional to the square of the OpAmp's differential input voltage. In this way, the currents of the OpAmp's input pairs are boosted, thus improving slew rate. Experimental results in 0.5 μm CMOS technology verify current and slew rate enhancement factors between 10 and 15 with less than 20% static current increase.
KW - Class AB Amplifiers
KW - CMOS Analog integrated circuits
KW - flipped voltage followers
KW - low-voltage low power design
UR - http://www.scopus.com/inward/record.url?scp=84946230888&partnerID=8YFLogxK
U2 - 10.1109/ISCAS.2015.7168618
DO - 10.1109/ISCAS.2015.7168618
M3 - Conference Contribution (Conference Proceeding)
AN - SCOPUS:84946230888
T3 - Proceedings - IEEE International Symposium on Circuits and Systems
SP - 253
EP - 256
BT - 2015 IEEE International Symposium on Circuits and Systems, ISCAS 2015
PB - Institute of Electrical and Electronics Engineers (IEEE)
T2 - IEEE International Symposium on Circuits and Systems, ISCAS 2015
Y2 - 24 May 2015 through 27 May 2015
ER -