Closed-Form Equations for Through-Silicon Via (TSV) Parasitics in 3-D Integrated Circuits (ICs)

Roshan Weerasekera, Dinesh B Pamunuwa, Matt Grange, Hannu Tenhunen, Li-Rong Zheng

Research output: Chapter in Book/Report/Conference proceedingConference Contribution (Conference Proceeding)

Original languageUndefined/Unknown
Title of host publicationProc. Special Interest Workshop on 3D Integration -- Design Automation and Test in Europe (DATE)
Publication statusPublished - 1 Apr 2009

Cite this

Weerasekera, R., Pamunuwa, D. B., Grange, M., Tenhunen, H., & Zheng, L-R. (2009). Closed-Form Equations for Through-Silicon Via (TSV) Parasitics in 3-D Integrated Circuits (ICs). In Proc. Special Interest Workshop on 3D Integration -- Design Automation and Test in Europe (DATE)