Closed-Loop Temperature-Controlled Power Cycling for Accelerated Degradation Monitoring of GaN Devices

Power cycling is an accelerated thermal stress test that is used to evaluate the longevity of power semiconductor devices. Repeated heating and cooling applies stress to material interfaces, eventually leading to device failure, typically after hundreds of thousands of cycles and several months. This paper describes a modified power cycling approach that is different from standardised methods in four key ways. First, it presents the use of high-power, sub-second heating phases to accelerate power cycling to approximately 200,000 cycles per week. Second, the heating process includes real-world switching stress, in contrast to conventional thermal methods. Third, the cycling parameters are carefully selected to produce a targeted temperature swing at specific potential failure locations, using an experimentally validated 3D thermal device model. Finally, device degradation is monitored during power cycling by intermittently characterising the device. Switching enables peak di/dt to serve as a junction temperature metric, providing input to a closed-loop temperature controller. A power cycling circuit is presented that allows hard switching at device ratings and power device characterisation, without desoldering. The interdependencies of heating power, cooling design, cycle time, and junction temperature swing are illustrated using two test configurations, both achieving a 100°C junction swing but differing in die-attach swing (56°C and 86°C). Devices are intermittently characterised during cycling, showing only single-digit % changes. In contrast, closed-loop controlled heating durations noticeably shift over time, signalling degradation, and begin to fluctuate several thousand cycles before failure, potentially warning of impending failure.