Cogeneration of Fast Motion Estimation Processors and Algorithms for Advanced Video Coding

JL Nunez-Yanez, Atukem Nabina, Eddie Hung, G Vafiadis

Research output: Contribution to journalArticle (Academic Journal)peer-review

15 Citations (Scopus)
257 Downloads (Pure)

Abstract

This paper presents a flexible and scalable motion estimation processor capable of supporting the processing requirements for high-definition (HD) video using the H.264 Advanced Video Codec, which is suited for FPGA implementation. Unlike most previous work, our core is optimized to execute all existing fast block matching algorithms, which we show to match or exceed the inter-frame prediction performance of traditional full-search approaches at the HD resolutions commonly in use today. Using our development tools, such algorithms can be described using a C-style syntax which is compiled into our custom instruction set. We show that different HD sequences exhibit different characteristics which necessitate a flexible and configurable solution when targeting embedded applications. This is supported in our core and toolset by allowing designers to modify the number of functional units to be instantiated. All processor instances remain binary compatible so recompilation of the motion estimation algorithm is not required. Due to this optimization process, it is possible to match the processing requirements of the selected motion estimation algorithm to the hardware microarchitecture leading to a very efficient implementation.
Translated title of the contributionCogeneration of Fast Motion Estimation Processors and Algorithms for Advanced Video Coding
Original languageEnglish
Pages (from-to)437-448
Number of pages12
JournalIEEE Transactions on Very Large Scale Integration (VLSI) Systems
Volume20
Issue number3
DOIs
Publication statusPublished - 10 Feb 2011

Keywords

  • Field-programmable gate array (FPGA)
  • H.264
  • motion estimation
  • reconfigurable processor
  • video coding

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