Abstract
Communicating process architecture can be used to build efficient multicore chips scaling to hundreds of processors. Concurrent processing, communications and input-output are supported directly by the instruction set of the cores and by the protoicol used in the on-chip interconect. Concurrent programs are compiled directly to the chip exploting novel compiler optimizations. The architecture supports a variety of programming techniques, ranging from statically configured process netwroks to dynamic reconfiguration and mobile processes.
| Original language | English |
|---|---|
| Pages (from-to) | 935-948 |
| Number of pages | 14 |
| Journal | Concurrency and Computation: Practice and Experience |
| Volume | 22 |
| Issue number | 8 |
| DOIs | |
| Publication status | Published - 23 Oct 2009 |
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