Compact modelling of Through-Silicon Vias (TSVs) in three-dimensional (3-D) integrated circuits

I D B Pamunuwa, R Weerasekera, M Grange, H Tenhunen, L-R. Zheng

Research output: Chapter in Book/Report/Conference proceedingConference Contribution (Conference Proceeding)

83 Citations (Scopus)

Abstract

Modeling parasitic parameters of Through-Silicon-Via (TSV) structures is essential in exploring electrical characteristics such as delay and signal integrity (SI) of circuits and interconnections in three-dimensional (3-D) integrated circuits (ICs). This paper presents a complete set of self-consistent equations including self and coupling terms for resistance, capacitance and inductance of various TSV structures. Further, a reduced-order electrical circuit model is proposed for isolated TSVs as well as bundled structures for delay and SI analysis, and extracted TSV parasitics are employed in Spectre simulations for performance evaluations. Critical issues in the performance modeling for design space exploration of 3-D ICs such as cross-talk induced switching pattern dependent delay variation and cross-talk on noise are discussed. The error in these metrics when using the proposed models as compared to a field solver is contained to a few percentage points.
Original languageEnglish
Title of host publicationIEEE International Conference on 3D System Integration
Place of PublicationSan Francisco, CA
PublisherInstitute of Electrical and Electronics Engineers (IEEE)
Pages1-8
Number of pages8
ISBN (Electronic) 978-1-4244-4512-7
ISBN (Print)978-1-4244-4511-0
DOIs
Publication statusPublished - 30 Sep 2009

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