TY - JOUR
T1 - Concurrent error detection for orthogonal latin squares encoders and syndrome computation
AU - Reviriego, Pedro
AU - Pontarelli, Salvatore
AU - Maestro, Juan Antonio
PY - 2013/1/4
Y1 - 2013/1/4
N2 - Error correction codes (ECCs) are commonly used to protect memories against errors. Among ECCs, orthogonal latin squares (OLS) codes have gained renewed interest for memory protection due to their modularity and the simplicity of the decoding algorithm that enables low delay implementations. An important issue is that when ECCs are used, the encoder and decoder circuits can also suffer errors. In this brief, a concurrent error detection technique for OLS codes encoders and syndrome computation is proposed and evaluated. The proposed method uses the properties of OLS codes to efficiently implement a parity prediction scheme that detects all errors that affect a single circuit node.
AB - Error correction codes (ECCs) are commonly used to protect memories against errors. Among ECCs, orthogonal latin squares (OLS) codes have gained renewed interest for memory protection due to their modularity and the simplicity of the decoding algorithm that enables low delay implementations. An important issue is that when ECCs are used, the encoder and decoder circuits can also suffer errors. In this brief, a concurrent error detection technique for OLS codes encoders and syndrome computation is proposed and evaluated. The proposed method uses the properties of OLS codes to efficiently implement a parity prediction scheme that detects all errors that affect a single circuit node.
KW - Concurrent error detection
KW - error correction codes (ECC)
KW - Latin squares
KW - majority logic decoding (MLD)
KW - memory
UR - http://www.scopus.com/inward/record.url?scp=84886596120&partnerID=8YFLogxK
U2 - 10.1109/TVLSI.2012.2230655
DO - 10.1109/TVLSI.2012.2230655
M3 - Article (Academic Journal)
AN - SCOPUS:84886596120
SN - 1063-8210
VL - 21
SP - 2334
EP - 2338
JO - IEEE Transactions on Very Large Scale Integration (VLSI) Systems
JF - IEEE Transactions on Very Large Scale Integration (VLSI) Systems
IS - 12
M1 - 6395842
ER -