Abstract
We investigate the performance improvement of a multithreaded MPEG-4 video encoder executing on a configurable, extensible, SoC multiprocessor. Architecture-level results indicate a significant reduction in the dynamic instruction count of the order of 83% for 16 processor contexts compared to the original single-thread implementation. We extended an open-source 32-bit RISC CPU to include hardware-based multi-processing primitives and associated support state and implemented a parametric, bus-based SoC multiprocessor as the target platform for the threaded video encoder. © 2005 IEEE.
| Translated title of the contribution | Configurable multiprocessors for high-performance MPEG-4 video coding |
|---|---|
| Original language | English |
| Title of host publication | IEEE Computer Society Annual Symposium on VLSI - New Frontiers in VLSI Design, Tampa, FL, United States |
| Publisher | IEEE Computer Society |
| Pages | 272 - 273 |
| Number of pages | 2 |
| ISBN (Print) | 076952365X |
| Publication status | Published - 11 May 2005 |