Configurable multiprocessors for high-performance MPEG-4 video coding

VA Chouliaras, TR Jacobs, Ashwin K Kumaraswamy, JL Nunez-Yanez

Research output: Chapter in Book/Report/Conference proceedingConference Contribution (Conference Proceeding)

Abstract

We investigate the performance improvement of a multithreaded MPEG-4 video encoder executing on a configurable, extensible, SoC multiprocessor. Architecture-level results indicate a significant reduction in the dynamic instruction count of the order of 83% for 16 processor contexts compared to the original single-thread implementation. We extended an open-source 32-bit RISC CPU to include hardware-based multi-processing primitives and associated support state and implemented a parametric, bus-based SoC multiprocessor as the target platform for the threaded video encoder. © 2005 IEEE.
Original languageEnglish
Title of host publicationIEEE Computer Society Annual Symposium on VLSI - New Frontiers in VLSI Design, Tampa, FL, United States
PublisherIEEE Computer Society
Pages272 - 273
Number of pages2
ISBN (Print)076952365X
Publication statusPublished - 11 May 2005

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    Chouliaras, VA., Jacobs, TR., Kumaraswamy, A. K., & Nunez-Yanez, JL. (2005). Configurable multiprocessors for high-performance MPEG-4 video coding. In IEEE Computer Society Annual Symposium on VLSI - New Frontiers in VLSI Design, Tampa, FL, United States (pp. 272 - 273). IEEE Computer Society.