Configurable multiprocessors for high-performance MPEG-4 video coding

VA Chouliaras; TR Jacobs; Ashwin K Kumaraswamy; JL Nunez-Yanez

Configurable multiprocessors for high-performance MPEG-4 video coding

VA Chouliaras, TR Jacobs, Ashwin K Kumaraswamy, JL Nunez-Yanez

Research output: Chapter in Book/Report/Conference proceeding › Conference Contribution (Conference Proceeding)

Abstract

We investigate the performance improvement of a multithreaded MPEG-4 video encoder executing on a configurable, extensible, SoC multiprocessor. Architecture-level results indicate a significant reduction in the dynamic instruction count of the order of 83% for 16 processor contexts compared to the original single-thread implementation. We extended an open-source 32-bit RISC CPU to include hardware-based multi-processing primitives and associated support state and implemented a parametric, bus-based SoC multiprocessor as the target platform for the threaded video encoder. © 2005 IEEE.

Translated title of the contribution	Configurable multiprocessors for high-performance MPEG-4 video coding
Original language	English
Title of host publication	IEEE Computer Society Annual Symposium on VLSI - New Frontiers in VLSI Design, Tampa, FL, United States
Publisher	IEEE Computer Society
Pages	272 - 273
Number of pages	2
ISBN (Print)	076952365X
Publication status	Published - 11 May 2005

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@inproceedings{64fd95581e5643549b11b628dc682c5f,

title = "Configurable multiprocessors for high-performance MPEG-4 video coding",

abstract = "We investigate the performance improvement of a multithreaded MPEG-4 video encoder executing on a configurable, extensible, SoC multiprocessor. Architecture-level results indicate a significant reduction in the dynamic instruction count of the order of 83\% for 16 processor contexts compared to the original single-thread implementation. We extended an open-source 32-bit RISC CPU to include hardware-based multi-processing primitives and associated support state and implemented a parametric, bus-based SoC multiprocessor as the target platform for the threaded video encoder. {\textcopyright} 2005 IEEE.",

author = "VA Chouliaras and TR Jacobs and Kumaraswamy, \{Ashwin K\} and JL Nunez-Yanez",

year = "2005",

month = may,

day = "11",

language = "English",

isbn = "076952365X",

pages = "272 -- 273",

booktitle = "IEEE Computer Society Annual Symposium on VLSI - New Frontiers in VLSI Design, Tampa, FL, United States",

publisher = "IEEE Computer Society",

address = "United States",

}

Configurable multiprocessors for high-performance MPEG-4 video coding. / Chouliaras, VA; Jacobs, TR; Kumaraswamy, Ashwin K et al.
IEEE Computer Society Annual Symposium on VLSI - New Frontiers in VLSI Design, Tampa, FL, United States. IEEE Computer Society, 2005. p. 272 - 273.

Research output: Chapter in Book/Report/Conference proceeding › Conference Contribution (Conference Proceeding)

TY - GEN

T1 - Configurable multiprocessors for high-performance MPEG-4 video coding

AU - Chouliaras, VA

AU - Jacobs, TR

AU - Kumaraswamy, Ashwin K

AU - Nunez-Yanez, JL

PY - 2005/5/11

Y1 - 2005/5/11

N2 - We investigate the performance improvement of a multithreaded MPEG-4 video encoder executing on a configurable, extensible, SoC multiprocessor. Architecture-level results indicate a significant reduction in the dynamic instruction count of the order of 83% for 16 processor contexts compared to the original single-thread implementation. We extended an open-source 32-bit RISC CPU to include hardware-based multi-processing primitives and associated support state and implemented a parametric, bus-based SoC multiprocessor as the target platform for the threaded video encoder. © 2005 IEEE.

AB - We investigate the performance improvement of a multithreaded MPEG-4 video encoder executing on a configurable, extensible, SoC multiprocessor. Architecture-level results indicate a significant reduction in the dynamic instruction count of the order of 83% for 16 processor contexts compared to the original single-thread implementation. We extended an open-source 32-bit RISC CPU to include hardware-based multi-processing primitives and associated support state and implemented a parametric, bus-based SoC multiprocessor as the target platform for the threaded video encoder. © 2005 IEEE.

M3 - Conference Contribution (Conference Proceeding)

SN - 076952365X

SP - 272

EP - 273

BT - IEEE Computer Society Annual Symposium on VLSI - New Frontiers in VLSI Design, Tampa, FL, United States

PB - IEEE Computer Society

ER -

Configurable multiprocessors for high-performance MPEG-4 video coding

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