Correlations Between Body Diode Pulsed Overcurrent Safe Operating Area, Short Circuit, and Avalanche Ruggedness in SiC MOSFETs

Power MOSFETs are sometimes taken outside their safe operating area (SOA). This can be during pulsed overcurrents, avalanche conduction mode during unclamped inductive switching (UIS) or short-circuit events. These conditions present different stresses to the device. In pulsed overcurrent conditions, the device is subject to overcurrents at low voltage; in UIS, the device is subject to overvoltage at low currents; and in short circuits, the device is subject to both. The ability of the MOSFET to withstand these conditions is a key robustness metric. How robustness under these three electrothermal shock events correlates with one another is yet to be investigated systematically. The objective of this article is to correlate these metrics in SiC MOSFETs by characterizing planar, asymmetric trench, and double-trench device structures. The critical energies to failure have been determined for all devices under the three undesired operating conditions, and correlations have been made. The maximum junction temperatures have been inferred by temperature-sensitive electrical parameters and confirmed with electrothermal simulations. The analysis in this article demonstrates that the critical avalanche and surge energies to failure are directly correlated, and they increase with stress duration. Furthermore, a tradeoff between short-circuit robustness and surge/avalanche robustness is observed based on device-specific on-state resistance.