CPCIe: A Compression-enabled PCIe Core for Energy and Performance Optimization

Mohd Amiruddin Bin Zainol; Jose L Nunez-Yanez

doi:10.1109/NORCHIP.2016.7792892

CPCIe: A Compression-enabled PCIe Core for Energy and Performance Optimization

Mohd Amiruddin Bin Zainol, Jose L Nunez-Yanez

Research output: Chapter in Book/Report/Conference proceeding › Conference Contribution (Conference Proceeding)

2 Citations (Scopus)

673 Downloads (Pure)

Abstract

PCIe is a hardware interface used in highperforming applications to move data from a central host and memory system to an accelerator such as a GPU or FPGA. In many memory bound applications, PCIe represents a bottleneck which limits the possible acceleration. In this paper, an opensource PCIe core is extended with a transparent layer of hardware compression/decompression with low latency and high throughput. The compressor/decompressor hardware operates on data values that match the width of the hardware interface and can be scaled up to higher parallelism. The results show an energy reduction of up to 84% in the PCIe transfers and up to 20% in the whole processing chain, thanks to the reduction in the number of bits that need to be moved over the power hungry wires that connect the main memory system to the accelerator in both directions. The overhead in terms of latency is maintained to a minimum and user selectable depending on the tolerances of the intended application.

Original language	English
Title of host publication	2016 IEEE Nordic Circuits and Systems Conference (NORCAS 2016)
Subtitle of host publication	Proceedings of a meeting held 1-2 December 2016, Copenhagen, Denmark
Publisher	Institute of Electrical and Electronics Engineers (IEEE)
Pages	127-132
Number of pages	6
ISBN (Electronic)	9781509010950
ISBN (Print)	9781509010967
DOIs	https://doi.org/10.1109/NORCHIP.2016.7792892
Publication status	Published - Feb 2017
Event	2nd IEEE Nordic Circuits and Systems Conference, NORCAS 2016 - Copenhagen, Denmark Duration: 1 Nov 2016 → 2 Nov 2016

Conference

Conference	2nd IEEE Nordic Circuits and Systems Conference, NORCAS 2016
Country/Territory	Denmark
City	Copenhagen
Period	1/11/16 → 2/11/16

Keywords

PCIe
FPGA
data compression
energy efficiency

UN SDGs

This output contributes to the following UN Sustainable Development Goals (SDGs)

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10.1109/NORCHIP.2016.7792892

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Bin Zainol, M. A., & Nunez-Yanez, J. L. (2017). CPCIe: A Compression-enabled PCIe Core for Energy and Performance Optimization. In 2016 IEEE Nordic Circuits and Systems Conference (NORCAS 2016): Proceedings of a meeting held 1-2 December 2016, Copenhagen, Denmark (pp. 127-132). Article 7792892 Institute of Electrical and Electronics Engineers (IEEE). https://doi.org/10.1109/NORCHIP.2016.7792892

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abstract = "PCIe is a hardware interface used in highperforming applications to move data from a central host and memory system to an accelerator such as a GPU or FPGA. In many memory bound applications, PCIe represents a bottleneck which limits the possible acceleration. In this paper, an opensource PCIe core is extended with a transparent layer of hardware compression/decompression with low latency and high throughput. The compressor/decompressor hardware operates on data values that match the width of the hardware interface and can be scaled up to higher parallelism. The results show an energy reduction of up to 84% in the PCIe transfers and up to 20% in the whole processing chain, thanks to the reduction in the number of bits that need to be moved over the power hungry wires that connect the main memory system to the accelerator in both directions. The overhead in terms of latency is maintained to a minimum and user selectable depending on the tolerances of the intended application.",

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author = "{Bin Zainol}, {Mohd Amiruddin} and Nunez-Yanez, {Jose L}",

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booktitle = "2016 IEEE Nordic Circuits and Systems Conference (NORCAS 2016)",

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Bin Zainol, MA & Nunez-Yanez, JL 2017, CPCIe: A Compression-enabled PCIe Core for Energy and Performance Optimization. in 2016 IEEE Nordic Circuits and Systems Conference (NORCAS 2016): Proceedings of a meeting held 1-2 December 2016, Copenhagen, Denmark., 7792892, Institute of Electrical and Electronics Engineers (IEEE), pp. 127-132, 2nd IEEE Nordic Circuits and Systems Conference, NORCAS 2016, Copenhagen, Denmark, 1/11/16. https://doi.org/10.1109/NORCHIP.2016.7792892

CPCIe: A Compression-enabled PCIe Core for Energy and Performance Optimization. / Bin Zainol, Mohd Amiruddin; Nunez-Yanez, Jose L.
2016 IEEE Nordic Circuits and Systems Conference (NORCAS 2016): Proceedings of a meeting held 1-2 December 2016, Copenhagen, Denmark. Institute of Electrical and Electronics Engineers (IEEE), 2017. p. 127-132 7792892.

Research output: Chapter in Book/Report/Conference proceeding › Conference Contribution (Conference Proceeding)

TY - GEN

T1 - CPCIe

T2 - 2nd IEEE Nordic Circuits and Systems Conference, NORCAS 2016

AU - Bin Zainol, Mohd Amiruddin

AU - Nunez-Yanez, Jose L

PY - 2017/2

Y1 - 2017/2

N2 - PCIe is a hardware interface used in highperforming applications to move data from a central host and memory system to an accelerator such as a GPU or FPGA. In many memory bound applications, PCIe represents a bottleneck which limits the possible acceleration. In this paper, an opensource PCIe core is extended with a transparent layer of hardware compression/decompression with low latency and high throughput. The compressor/decompressor hardware operates on data values that match the width of the hardware interface and can be scaled up to higher parallelism. The results show an energy reduction of up to 84% in the PCIe transfers and up to 20% in the whole processing chain, thanks to the reduction in the number of bits that need to be moved over the power hungry wires that connect the main memory system to the accelerator in both directions. The overhead in terms of latency is maintained to a minimum and user selectable depending on the tolerances of the intended application.

AB - PCIe is a hardware interface used in highperforming applications to move data from a central host and memory system to an accelerator such as a GPU or FPGA. In many memory bound applications, PCIe represents a bottleneck which limits the possible acceleration. In this paper, an opensource PCIe core is extended with a transparent layer of hardware compression/decompression with low latency and high throughput. The compressor/decompressor hardware operates on data values that match the width of the hardware interface and can be scaled up to higher parallelism. The results show an energy reduction of up to 84% in the PCIe transfers and up to 20% in the whole processing chain, thanks to the reduction in the number of bits that need to be moved over the power hungry wires that connect the main memory system to the accelerator in both directions. The overhead in terms of latency is maintained to a minimum and user selectable depending on the tolerances of the intended application.

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Bin Zainol MA, Nunez-Yanez JL. CPCIe: A Compression-enabled PCIe Core for Energy and Performance Optimization. In 2016 IEEE Nordic Circuits and Systems Conference (NORCAS 2016): Proceedings of a meeting held 1-2 December 2016, Copenhagen, Denmark. Institute of Electrical and Electronics Engineers (IEEE). 2017. p. 127-132. 7792892 Epub 2016 Dec 22. doi: 10.1109/NORCHIP.2016.7792892

CPCIe: A Compression-enabled PCIe Core for Energy and Performance Optimization

Abstract

Conference

Keywords

UN SDGs

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Energy Proportional Computing With Heterogeneous and Reconfigurable Processors (ENPOWER)

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CPCIe: A Compression-enabled PCIe Core for Energy and Performance Optimization

Abstract

Conference

Keywords

UN SDGs

Access to Document

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Other files and links

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Energy Proportional Computing With Heterogeneous and Reconfigurable Processors (ENPOWER)

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