Degradation Analysis of Planar, Symmetrical and Asymmetrical Trench SiC MOSFETs Under Repetitive Short Circuit Impulses

Renze Yu, Saeed Jahdi*, Phil Mellor, Li Liu, Juefei Yang, Chengjun Shen, Olayiwola Alatise, Jose Ortiz-Gonzalez

*Corresponding author for this work

Research output: Contribution to journalArticle (Academic Journal)peer-review

22 Citations (Scopus)
247 Downloads (Pure)

Abstract

In this article, the reliability of planar, symmetrical, and asymmetrical trench SiC MOSFETs is analysed under repetitive short circuit impulses at 300 and 450 K. Both static and dynamic parameters are measured to characterize the degradation pattern of the three MOSFET structures. The degradation mechanisms are analyzed and the internal electro-thermal behavior of MOSFETs is revealed through TCAD models. It has been found out that there is minor degradation for planar SiC devices under both test conditions. The symmetrical trench SiC MOSFET has the lowest reliability, which fails after 200 and 80 cycles at room and elevated temperature. The asymmetrical trench SiC MOSFET has slightly higher reliability, failing after 1500 cycles and 500 cycles at room and elevated temperature, respectively. A comprehensive range of measurements until failure and the corresponding Silvaco TCAD analysis confirms that for both trench SiC MOSFETs, the deterioration of the gate oxide is responsible for the degradations and device failure. The higher the temperature, the higher electro-thermomechanical stress the devices suffer.
Original languageEnglish
Pages (from-to)10933-10946
Number of pages14
JournalIEEE Transactions on Power Electronics
Volume38
Issue number9
DOIs
Publication statusPublished - 28 Jun 2023

Bibliographical note

Funding Information:
This work was supported by the U.K. Engineering and Physical Research Council under the Supergen Energy Networks Hub initiative underGrant EP/S00078X/2.

Publisher Copyright:
© 1986-2012 IEEE.

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