Degradation Pattern of Parallel Symmetrical and Asymmetrical Double-Trench SiC MOSFETs under Repetitive Short Circuits

Renze Yu; Saeed Jahdi

doi:10.30420/566091111

Degradation Pattern of Parallel Symmetrical and Asymmetrical Double-Trench SiC MOSFETs under Repetitive Short Circuits

Renze Yu
, Saeed Jahdi^*

^*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceeding › Conference Contribution (Conference Proceeding)

54 Downloads (Pure)

Abstract

In practice, SiC MOSFET chips are often parallel-connected to promote the power rating. However, due to the potentially unequal circuit parameter and temperature distribution inside the power module, parallel devices suffer from different electrothermal stress, which may result in long-term reliability challenges. In this paper, the short circuit performance of parallel-connected Planar, Symmetrical and Asymmetrical Double-Trench SiC MOSFETs have been investigated. The impact of gate resistance and case temperature difference on current distribution of parallel SiC MOSFETs have been analyzed. The degradation pattern of key parameters of three types of devices have been studied.

Original language	English
Title of host publication	PCIM Europe 2023
Subtitle of host publication	International Exhibition and Conference for Power Electronics, Intelligent Motion, Renewable Energy and Energy Management
Place of Publication	Nuremberg, Germany
Publisher	VDE Verlag
Pages	804-809
Number of pages	6
ISBN (Print)	978-3-8007-6091-6
DOIs	https://doi.org/10.30420/566091111
Publication status	Published - 4 Jul 2023

Access to Document

10.30420/566091111

Full-text PDF (accepted author manuscript)
This is the accepted author manuscript (AAM). The final published version (version of record) is available online via VDE at https://doi.org/10.30420/566091111. Please refer to any applicable terms of use of the publisher.
Accepted author manuscript, 9.17 MB

https://ieeexplore.ieee.org/document/10173210

Handle.net

Persistent link

Failure and Degradation Analysis of Planar and Trench SiC MOSFETs Under Repetitive Short Circuit Stress
Yu, R. (Author), Jahdi, S. (Supervisor) & Mellor, P. (Supervisor), 17 Jun 2025
Student thesis: Doctoral Thesis › Doctor of Philosophy (PhD)

File

Cite this

@inproceedings{134524ddd91b4fcfbe747ca7f77cab31,

title = "Degradation Pattern of Parallel Symmetrical and Asymmetrical Double-Trench SiC MOSFETs under Repetitive Short Circuits",

abstract = "In practice, SiC MOSFET chips are often parallel-connected to promote the power rating. However, due to the potentially unequal circuit parameter and temperature distribution inside the power module, parallel devices suffer from different electrothermal stress, which may result in long-term reliability challenges. In this paper, the short circuit performance of parallel-connected Planar, Symmetrical and Asymmetrical Double-Trench SiC MOSFETs have been investigated. The impact of gate resistance and case temperature difference on current distribution of parallel SiC MOSFETs have been analyzed. The degradation pattern of key parameters of three types of devices have been studied.",

author = "Renze Yu and Saeed Jahdi",

year = "2023",

month = jul,

day = "4",

doi = "10.30420/566091111",

language = "English",

isbn = "978-3-8007-6091-6",

pages = "804--809",

booktitle = "PCIM Europe 2023",

publisher = "VDE Verlag",

}

Degradation Pattern of Parallel Symmetrical and Asymmetrical Double-Trench SiC MOSFETs under Repetitive Short Circuits. / Yu, Renze ; Jahdi, Saeed.
PCIM Europe 2023: International Exhibition and Conference for Power Electronics, Intelligent Motion, Renewable Energy and Energy Management. Nuremberg, Germany: VDE Verlag, 2023. p. 804-809.

Research output: Chapter in Book/Report/Conference proceeding › Conference Contribution (Conference Proceeding)

TY - GEN

T1 - Degradation Pattern of Parallel Symmetrical and Asymmetrical Double-Trench SiC MOSFETs under Repetitive Short Circuits

AU - Yu, Renze

AU - Jahdi, Saeed

PY - 2023/7/4

Y1 - 2023/7/4

N2 - In practice, SiC MOSFET chips are often parallel-connected to promote the power rating. However, due to the potentially unequal circuit parameter and temperature distribution inside the power module, parallel devices suffer from different electrothermal stress, which may result in long-term reliability challenges. In this paper, the short circuit performance of parallel-connected Planar, Symmetrical and Asymmetrical Double-Trench SiC MOSFETs have been investigated. The impact of gate resistance and case temperature difference on current distribution of parallel SiC MOSFETs have been analyzed. The degradation pattern of key parameters of three types of devices have been studied.

AB - In practice, SiC MOSFET chips are often parallel-connected to promote the power rating. However, due to the potentially unequal circuit parameter and temperature distribution inside the power module, parallel devices suffer from different electrothermal stress, which may result in long-term reliability challenges. In this paper, the short circuit performance of parallel-connected Planar, Symmetrical and Asymmetrical Double-Trench SiC MOSFETs have been investigated. The impact of gate resistance and case temperature difference on current distribution of parallel SiC MOSFETs have been analyzed. The degradation pattern of key parameters of three types of devices have been studied.

U2 - 10.30420/566091111

DO - 10.30420/566091111

M3 - Conference Contribution (Conference Proceeding)

SN - 978-3-8007-6091-6

SP - 804

EP - 809

BT - PCIM Europe 2023

PB - VDE Verlag

CY - Nuremberg, Germany

ER -

Degradation Pattern of Parallel Symmetrical and Asymmetrical Double-Trench SiC MOSFETs under Repetitive Short Circuits

Abstract

Access to Document

Handle.net

Fingerprint

Student theses

Failure and Degradation Analysis of Planar and Trench SiC MOSFETs Under Repetitive Short Circuit Stress

Cite this