@inproceedings{8a699631e7334262adb4f6b2fbe8983a,
title = "Delay-Balanced Smart Repeaters for On-Chip Global Signaling",
keywords = "driver circuits, interference suppression, jitter, repeaters, 0.18 micron, 1 Gbits/s, assistant driver, delay-balanced smart repeaters, higher effective load capacitance, jitter reduction, lower effective load capacitance, main driver, on-chip global signaling, smart driver, Capacitance, Energy consumption, Integrated circuit interconnections, Jitter, Propagation delay, Repeaters, Signal design, Switches, System-on-a-chip, Wire",
author = "Roshan Weerasekera and Dinesh Pamunuwa and Li-rong Zheng and Hannu Tenhunen",
year = "2007",
month = jan,
day = "1",
doi = "10.1109/VLSID.2007.62",
language = "Undefined/Unknown",
pages = "308--313",
booktitle = "20th International Conference on VLSI Design held jointly with 6th International Conference on Embedded Systems (VLSID'07)",
}