Delay-Balanced Smart Repeaters for On-Chip Global Signaling

Roshan Weerasekera, Dinesh Pamunuwa, Li-Rong Zheng, Hannu Tenhunen

Research output: Chapter in Book/Report/Conference proceedingConference Contribution (Conference Proceeding)

Original languageUndefined/Unknown
Title of host publicationProc. IEEE International Conference on VLSI Design
Pages308-313
Number of pages6
DOIs
Publication statusPublished - 1 Jan 2007

Keywords

  • driver circuits
  • interference suppression
  • jitter
  • repeaters
  • 0.18 micron
  • 1 Gbits/s
  • assistant driver
  • delay-balanced smart repeaters
  • higher effective load capacitance
  • jitter reduction
  • lower effective load capacitance
  • main driver
  • on-chip global signaling
  • smart driver
  • Capacitance
  • Energy consumption
  • Integrated circuit interconnections
  • Jitter
  • Propagation delay
  • Repeaters
  • Signal design
  • Switches
  • System-on-a-chip
  • Wire

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