Delay-Balanced Smart Repeaters for On-Chip Global Signaling

Roshan Weerasekera; Dinesh Pamunuwa; Li-Rong Zheng; Hannu Tenhunen

doi:10.1109/VLSID.2007.62

Delay-Balanced Smart Repeaters for On-Chip Global Signaling

Roshan Weerasekera, Dinesh Pamunuwa, Li-Rong Zheng, Hannu Tenhunen

Research output: Chapter in Book/Report/Conference proceeding › Conference Contribution (Conference Proceeding)

Original language	Undefined/Unknown
Title of host publication	Proc. IEEE International Conference on VLSI Design
Pages	308-313
Number of pages	6
DOIs	https://doi.org/10.1109/VLSID.2007.62
Publication status	Published - 1 Jan 2007

Keywords

driver circuits
interference suppression
jitter
repeaters
0.18 micron
1 Gbits/s
assistant driver
delay-balanced smart repeaters
higher effective load capacitance
jitter reduction
lower effective load capacitance
main driver
on-chip global signaling
smart driver
Capacitance
Energy consumption
Integrated circuit interconnections
Jitter
Propagation delay
Repeaters
Signal design
Switches
System-on-a-chip
Wire

Access to Document

10.1109/VLSID.2007.62

Cite this

@inproceedings{8a699631e7334262adb4f6b2fbe8983a,

title = "Delay-Balanced Smart Repeaters for On-Chip Global Signaling",

keywords = "driver circuits, interference suppression, jitter, repeaters, 0.18 micron, 1 Gbits/s, assistant driver, delay-balanced smart repeaters, higher effective load capacitance, jitter reduction, lower effective load capacitance, main driver, on-chip global signaling, smart driver, Capacitance, Energy consumption, Integrated circuit interconnections, Jitter, Propagation delay, Repeaters, Signal design, Switches, System-on-a-chip, Wire",

author = "Roshan Weerasekera and Dinesh Pamunuwa and Li-Rong Zheng and Hannu Tenhunen",

year = "2007",

month = jan,

day = "1",

doi = "10.1109/VLSID.2007.62",

language = "Undefined/Unknown",

pages = "308--313",

booktitle = "Proc. IEEE International Conference on VLSI Design",

}

TY - GEN

T1 - Delay-Balanced Smart Repeaters for On-Chip Global Signaling

AU - Weerasekera, Roshan

AU - Pamunuwa, Dinesh

AU - Zheng, Li-Rong

AU - Tenhunen, Hannu

PY - 2007/1/1

Y1 - 2007/1/1

KW - driver circuits

KW - interference suppression

KW - jitter

KW - repeaters

KW - 0.18 micron

KW - 1 Gbits/s

KW - assistant driver

KW - delay-balanced smart repeaters

KW - higher effective load capacitance

KW - jitter reduction

KW - lower effective load capacitance

KW - main driver

KW - on-chip global signaling

KW - smart driver

KW - Capacitance

KW - Energy consumption

KW - Integrated circuit interconnections

KW - Jitter

KW - Propagation delay

KW - Repeaters

KW - Signal design

KW - Switches

KW - System-on-a-chip

KW - Wire

U2 - 10.1109/VLSID.2007.62

DO - 10.1109/VLSID.2007.62

M3 - Conference Contribution (Conference Proceeding)

SP - 308

EP - 313

BT - Proc. IEEE International Conference on VLSI Design

ER -