Design and implementation of a high-performance and silicon efficient arithmetic coding accelerator for the H.264 advanced video codec

JL Nunez-Yanez, VA Chouliaras

Research output: Chapter in Book/Report/Conference proceedingConference Contribution (Conference Proceeding)

13 Citations (Scopus)
Translated title of the contributionDesign and implementation of a high-performance and silicon efficient arithmetic coding accelerator for the H.264 advanced video codec
Original languageEnglish
Title of host publication16th International Conference on Application-Specific Systems, Architecture and Processors, Greece
PublisherInstitute of Electrical and Electronics Engineers (IEEE)
Pages411 - 416
Number of pages6
Volume1
ISBN (Print)0769524079
DOIs
Publication statusPublished - 23 Jul 2005

Bibliographical note

Conference Proceedings/Title of Journal: 16th International Conference on Application-Specific Systems, Architecture and Processors
Conference Organiser: IEEE

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