Design and implementation of a lossless parallel high-speed data compression system

M Milward, JL Nunez-Yanez, D Mulvaney

Research output: Contribution to journalArticle (Academic Journal)peer-review

7 Citations (Scopus)

Abstract

Logic density increases have made feasible the implementation of multiprocessor systems able to meet the intensive data processing demands of highly concurrent systems. We describe the research and hardware implementation of a high-performance parallel multicompressor chip. A detailed investigation into the performances of alternative input and output routing strategies for realistic data sets demonstrate that the design of parallel compression devices involves important trade offs that affect compression performance, latency, and throughput. The most promising approach is implemented into FPGA hardware and is shown to provide a scalable compression solution at throughputs able to cope with the demands of modern high-bandwidth applications.
Translated title of the contributionDesign and implementation of a lossless parallel high-speed data compression system
Original languageEnglish
Pages (from-to)481-490
Number of pages10
JournalIEEE Transactions on Parallel and Distributed Systems
Volume15
Issue number6
DOIs
Publication statusPublished - Jun 2004

Bibliographical note

Publisher: IEEE

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