This paper presents the investigation of a new equaliser algorithm and architecture optimised for low cost FPGA implementation. The design was performed as part of the ESPRIT WINHOME project and is fully compliant with the European third generation HIPERLAN/1 wireless LAN standard. The equaliser supports GMSK modulation at an instantaneous transmission data-rate of just under 24 Mbits/s. In this paper the equaliser algorithm and pipelined DLMS DFE architecture is presented. Issues such as signal quantisation, bit and frame synchronisation and frequency offset correction are discussed in detail. The final structure is shown to achieve considerable hardware simplification together with improved performance when compared to a standard implementation of the complex LMS equaliser.
|Pages||300 - 304|
|Publication status||Published - May 1999|
Bibliographical noteSponsorship: This work was performed as part of the ESPRIT
WINHOME project (25048).
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Name of Conference: 49th Vehicular Technology Conference 1999 (VTC 1999-Spring)
Venue of Conference: Houston, TX
Sun, Y., Nix, AR., Bull, D., Milford, D., de Beauchesne, H., Sperling, R., & Rouzet, PH. (1999). Design of a novel delayed LMS decision feedback equaliser for HIPERLAN/1 FPGA implementation. 300 - 304. https://doi.org/10.1109/VETEC.1999.778065