Design of a Novel Delayed LMS Decision Feedback Equalizer for Hiperlan/1 FPGA ImplementationIB

Y Sun, AR Nix, DR Bull

Research output: Chapter in Book/Report/Conference proceedingConference Contribution (Conference Proceeding)

Translated title of the contributionDesign of a Novel Delayed LMS Decision Feedback Equalizer for Hiperlan/1 FPGA ImplementationIB
Original languageEnglish
Title of host publicationProceedings of the 49th IEEE Vehicular Technology Conference
Pages300 - 304
Volume1-3
Publication statusPublished - 1999

Bibliographical note

Other: Chapter 500

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