Design of a Novel Delayed LMS Decision Feedback Equalizer for Hiperlan/1 FPGA ImplementationIB

Y Sun, AR Nix, DR Bull

Research output: Chapter in Book/Report/Conference proceeding › Conference Contribution (Conference Proceeding)

Translated title of the contribution	Design of a Novel Delayed LMS Decision Feedback Equalizer for Hiperlan/1 FPGA ImplementationIB
Original language	English
Title of host publication	Proceedings of the 49th IEEE Vehicular Technology Conference
Pages	300 - 304
Volume	1-3
Publication status	Published - 1999

Other: Chapter 500

Handle.net

@inproceedings{c6e70e0b8499484cab1787df290a2934,

title = "Design of a Novel Delayed LMS Decision Feedback Equalizer for Hiperlan/1 FPGA ImplementationIB",

author = "Y Sun and AR Nix and DR Bull",

note = "Other: Chapter 500",

year = "1999",

language = "English",

volume = "1-3",

pages = "300 -- 304",

booktitle = "Proceedings of the 49th IEEE Vehicular Technology Conference",

}