The addition of custom vector instructions to the G.729A speech coding algorithm is shown to reduce significantly its computational complexity. The identified vector extensions are implemented in the form of a configurable vector accelerator, tightly coupled to a 32 bit Sparc V8-compliant reduced instruction set (RISC) processor. Architectural simulation demonstrates that a reduction in complexity of up 60%, for a vector length of sixteen 16 bit elements, is achievable in current VLSI technology.
|Translated title of the contribution||Development of custom vector accelerator for high-performance speech coding|
|Article number||Issue 24|
|Pages (from-to)||1559 - 1561|
|Number of pages||3|
|Publication status||Published - Nov 2004|