Digital Signal Processing Implementation Using the TMS320C6000 DSP Platform

Research output: Book/ReportAuthored book


Digital signal processing techniques are now so powerful that sometimes it is extremely difficult, if not impossible, for analogue signal processing to achieve the same or closer performance. Added to this, digital signal processors are very affordable and include good development tools and support. This is sufficient to explain the growing number of areas of application for DSP, including motor drives, communications, biomedical instrumentation and automotive applications.

Having dealt for some time with undergraduate and postgraduate students, researchers and digital signal processor users in general, I have found that first-time users of DSP find a barrier obstructing them in progressing from theory to the full implementation of algorithms.

When it comes to implementing an algorithm many questions arise, questions such as:

Which processor to use - fixed or floating point?
Which manufacturer to choose?
Which application hardware to use?
How many I/O interfaces are needed and how fast should they be?
When these questions are answered, more questions arise regarding the implementation on the specific processor and hardware selected. In this book, use of the TMS320C6000 will be justified, and the hardware and complete implementation of selected algorithms will be dealt with in detail. Material used for the teaching of undergraduate and postgraduate students, along with laboratory experiments, are used to demonstrate and simplify the transition from theory to the full implementation on the TMS320C6201 processor.

This book is divided into nine chapters. Chapters2and 3 are very important and it is advisable that they are well understood before progressing onto subsequent chapters.

Chapter 1 Introduction
This introductory chapter provides the reader with general knowledge on general-purpose DSP processors and also provides an up-to-date TMS320 roadmap showing the evolution of Texas Instruments' DSP chips in terms of processing power.

Chapter 2 The TMS320C62xxlC67xx architecture
The objective of this chapter is to provide a comprehensive description of the 'C6x architecture. This includes a detailed description of the Central Processing Unit (CPU) and program control along with an overview of the memory organisation, serial ports, boot function and internal timer.

Chapter 3 Software development tools and TMS32OC6201 EVM overview
This chapter is divided into three main parts. The first part describes the software development tools, the second part describes the Evaluation Module (EVM) and, finally, the third part describes the codec, and use of interrupts along with some useful programs for testing the TMS320C6201 EVM.

Chapter 4 Software optimisation
To introduce the need for code optimisation, this chapter starts by developing the concept of pipelining. Since the TMS320C62xx and the TMS320C67xx each have eight units, which are dedicated to different operations, and since different instructions can have different latencies, the programmer or the tools are left with the burden of scheduling the code. Backed by examples, this chapter explains the different techniques used to optimise DSP code on these processors.

Chapter 5 Finite Impulse Response (FIR) filter implementation
The purpose of this chapter is twofold. Primarily, it shows how to design an FIR filter and implement it on the TMS320C62xx processor, and secondly, it shows how to optimise the code as discussed in Chapter 4. This chapter discusses the interface between C and assembly, how to use intrinsics, and how to put into practice material that has been covered in the previous chapters.

Chapter 6 Infinite Impulse Response (IIR) filter implementation
This chapter introduces the IIR filters and describes two popular design methods, that is the bilinear and the impulse invariant methods. Step by step, this chapter shows the procedures necessary to implement typical IIR filters specified by their transfer functions. Finally, this chapter provides complete implementation of an IIR filter in C language, assembly and linear assembly, and shows how to interface C with linear assembly.

Chapter 7 Adaptive filter implementation
This chapter starts by introducing the need for an adaptive filter in communications. It then shows how to calculate the filter coefficients using the Mean Square Error (MSE) criterion, exposes the Least Mean Square (LMS) algorithm and, finally, shows how the LMS algorithm is implemented in both C and assembly.

Chapter 8 Goertzel algorithm implementation
This chapter deals with Dual Tone Multi-Frequency (DTMF) detection and provides a practical example of the Goertzel algorithm. This chapter also shows how to produce optimised code by the pen and paper method, describes linear assembly and demonstrates how to program the Direct Memory Access (DMA).

Chapter 9 Implementation of the Discrete Cosine Transform
This chapter starts by introducing the need for video compression to reduce the channel bandwidth requirement, then explains the Joint Photographic Experts Group (JPEG) image codec. This includes a detailed discussion and the implementation of the Discrete Cosine Transform (DCT) and Inverse Discrete Cosine Transform (IDCT) and concentrates on their optimisation. An explanation of the PC-DSP communication via the PCI bus is also provided.
Original languageEnglish
Place of Publication Boston, MA,
PublisherAddison-Wesley Longman Publishing Co., Inc.
Number of pages234
ISBN (Print)0201619164
Publication statusPublished - 21 Feb 2000


  • DSP implementation
  • DSP algorithms
  • Digital signal processing
  • digital signal processing chips


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