Early Selection of System Implementation Choice among SoC, SoP and 3-D Integration

Roshan Weerasekera; Li-Rong Zheng; Dinesh Pamunuwa; Hannu Tenhunen

doi:10.1109/SOCC.2007.4545455

Early Selection of System Implementation Choice among SoC, SoP and 3-D Integration

Roshan Weerasekera, Li-Rong Zheng, Dinesh Pamunuwa, Hannu Tenhunen

Research output: Chapter in Book/Report/Conference proceeding › Conference Contribution (Conference Proceeding)

Abstract

Recently there is a tendency for shifting the planar SoC single-chip solutions to different alternative options as tiled silicon and single-level embedded modules as well as 3-D integration, and the designers confronted with several system design options. To get a true improvement in performance, a very careful analysis using detailed models at different hierarchical levels is crucial. In this work, we present a cohesive analysis of the technological, cost and performance trade-offs for implementing digital and mixed-mode systems considering the choices between 2-D and 3-D integration and their ramifications.

Original language	Undefined/Unknown
Title of host publication	Proc. IEEE International Conference on Systems-on-Chip (SOC)
Pages	187-190
Number of pages	4
DOIs	https://doi.org/10.1109/SOCC.2007.4545455
Publication status	Published - 1 Sept 2007

Research Groups and Themes

Photonics and Quantum

Keywords

Assembly
Costs
Performance analysis
Power system modeling
Shape
Silicon
Stacking
System analysis and design
Temperature
Wafer bonding

Access to Document

10.1109/SOCC.2007.4545455

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Persistent link

Cite this

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title = "Early Selection of System Implementation Choice among SoC, SoP and 3-D Integration",

abstract = "Recently there is a tendency for shifting the planar SoC single-chip solutions to different alternative options as tiled silicon and single-level embedded modules as well as 3-D integration, and the designers confronted with several system design options. To get a true improvement in performance, a very careful analysis using detailed models at different hierarchical levels is crucial. In this work, we present a cohesive analysis of the technological, cost and performance trade-offs for implementing digital and mixed-mode systems considering the choices between 2-D and 3-D integration and their ramifications.",

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AU - Weerasekera, Roshan

AU - Zheng, Li-Rong

AU - Pamunuwa, Dinesh

AU - Tenhunen, Hannu

PY - 2007/9/1

Y1 - 2007/9/1

N2 - Recently there is a tendency for shifting the planar SoC single-chip solutions to different alternative options as tiled silicon and single-level embedded modules as well as 3-D integration, and the designers confronted with several system design options. To get a true improvement in performance, a very careful analysis using detailed models at different hierarchical levels is crucial. In this work, we present a cohesive analysis of the technological, cost and performance trade-offs for implementing digital and mixed-mode systems considering the choices between 2-D and 3-D integration and their ramifications.

AB - Recently there is a tendency for shifting the planar SoC single-chip solutions to different alternative options as tiled silicon and single-level embedded modules as well as 3-D integration, and the designers confronted with several system design options. To get a true improvement in performance, a very careful analysis using detailed models at different hierarchical levels is crucial. In this work, we present a cohesive analysis of the technological, cost and performance trade-offs for implementing digital and mixed-mode systems considering the choices between 2-D and 3-D integration and their ramifications.

KW - Assembly

KW - Costs

KW - Performance analysis

KW - Power system modeling

KW - Shape

KW - Silicon

KW - Stacking

KW - System analysis and design

KW - Temperature

KW - Wafer bonding

U2 - 10.1109/SOCC.2007.4545455

DO - 10.1109/SOCC.2007.4545455

M3 - Conference Contribution (Conference Proceeding)

SP - 187

EP - 190

BT - Proc. IEEE International Conference on Systems-on-Chip (SOC)

ER -