Recently there is a tendency for shifting the planar SoC single-chip solutions to different alternative options as tiled silicon and single-level embedded modules as well as 3-D integration, and the designers confronted with several system design options. To get a true improvement in performance, a very careful analysis using detailed models at different hierarchical levels is crucial. In this work, we present a cohesive analysis of the technological, cost and performance trade-offs for implementing digital and mixed-mode systems considering the choices between 2-D and 3-D integration and their ramifications.
|Title of host publication||Proc. IEEE International Conference on Systems-on-Chip (SOC)|
|Number of pages||4|
|Publication status||Published - 1 Sep 2007|
- Performance analysis
- Power system modeling
- System analysis and design
- Wafer bonding