| Translated title of the contribution | Easily Testable Implementation for Bit Parallel Multipliers in GF (2m) |
|---|---|
| Original language | English |
| Title of host publication | IEEE High-Level Design Validation and Test Workshop |
| Publication status | Published - 2006 |
Easily Testable Implementation for Bit Parallel Multipliers in GF (2m)
H Rahaman, J Matthew, AM Jabir, DK Pradhan
Research output: Chapter in Book/Report/Conference proceeding › Conference Contribution (Conference Proceeding)
7
Citations
(Scopus)