Easily Testable Implementation for Bit Parallel Multipliers in GF(2m)

H Rahaman; Jimson Mathew; Pradhan Dhiraj; A.M Jabir

Easily Testable Implementation for Bit Parallel Multipliers in GF(2m)

H Rahaman, Jimson Mathew, Pradhan Dhiraj, A.M Jabir

Department of Computer Science

Research output: Chapter in Book/Report/Conference proceeding › Conference Contribution (Conference Proceeding)

Translated title of the contribution	Easily Testable Implementation for Bit Parallel Multipliers in GF(2m)
Original language	English
Title of host publication	IEEE International High Level Design Validation and Test Workshop(HLDVT)
Publisher	Institute of Electrical and Electronics Engineers (IEEE)
Publication status	Published - 2006

Bibliographical note

Other page information: -
Conference Proceedings/Title of Journal: IEEE International High Level Design Validation and Test Workshop(HLDVT)
Other identifier: 2000640

Access to Document

http://www.cs.bris.ac.uk/Publications/pub_master.jsp?id=2000640

Handle.net

Persistent link

Cite this

@inproceedings{c12dab828ebe42168694f2c2fa0f1046,

title = "Easily Testable Implementation for Bit Parallel Multipliers in GF(2m)",

author = "H Rahaman and Jimson Mathew and Pradhan Dhiraj and A.M Jabir",

note = "Other page information: - Conference Proceedings/Title of Journal: IEEE International High Level Design Validation and Test Workshop(HLDVT) Other identifier: 2000640",

year = "2006",

language = "English",

booktitle = "IEEE International High Level Design Validation and Test Workshop(HLDVT)",

publisher = "Institute of Electrical and Electronics Engineers (IEEE)",

address = "United States",

}

Easily Testable Implementation for Bit Parallel Multipliers in GF(2m). / Rahaman, H; Mathew, Jimson; Dhiraj, Pradhan et al.
IEEE International High Level Design Validation and Test Workshop(HLDVT). Institute of Electrical and Electronics Engineers (IEEE), 2006.

Research output: Chapter in Book/Report/Conference proceeding › Conference Contribution (Conference Proceeding)

TY - GEN

T1 - Easily Testable Implementation for Bit Parallel Multipliers in GF(2m)

AU - Rahaman, H

AU - Mathew, Jimson

AU - Dhiraj, Pradhan

AU - Jabir, A.M

N1 - Other page information: - Conference Proceedings/Title of Journal: IEEE International High Level Design Validation and Test Workshop(HLDVT) Other identifier: 2000640

PY - 2006

Y1 - 2006

M3 - Conference Contribution (Conference Proceeding)

BT - IEEE International High Level Design Validation and Test Workshop(HLDVT)

PB - Institute of Electrical and Electronics Engineers (IEEE)

ER -