Easily Testable Implementation for Bit Parallel Multipliers in GF(2m)

H Rahaman, Jimson Mathew, Pradhan Dhiraj, A.M Jabir

Research output: Chapter in Book/Report/Conference proceedingConference Contribution (Conference Proceeding)

Translated title of the contributionEasily Testable Implementation for Bit Parallel Multipliers in GF(2m)
Original languageEnglish
Title of host publicationIEEE International High Level Design Validation and Test Workshop(HLDVT)
PublisherInstitute of Electrical and Electronics Engineers (IEEE)
Publication statusPublished - 2006

Bibliographical note

Other page information: -
Conference Proceedings/Title of Journal: IEEE International High Level Design Validation and Test Workshop(HLDVT)
Other identifier: 2000640

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