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A novel design methodology for test pattern generation in built-in self-test (BIST) is proposed. Experimental results are presented to demonstrate how a fault in the test pattern generator (TPG) itself can have serious consequences, a problem that has not been investigated. A solution is presented here, where the faults and errors in the generator itself are detected during the test in the TPG itself. This provides several major advantages, including the ability to distinguish between TPG and circuit under test (CUT) faults. In addition, this will ensure that there is no loss of fault coverage for the CUT caused by a fault in the TPG. Two different design methodologies are presented: The first guarantees all single fault/error detection, the second capable of detecting multiple faults and errors. The proposed linear feedback shift registers (LFSRs) do not have additional hardware overhead. Importantly, the test patterns generated have the potential to achieve superior fault coverage for both stuck-at and transition faults.
|Translated title of the contribution||EBIST: a novel test generator with built-in fault detection capability|
|Pages (from-to)||1457 - 1466|
|Number of pages||10|
|Journal||IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems|
|Publication status||Published - Sep 2005|
Bibliographical notePublisher: IEEE
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- 1 Finished
Pradhan, D. K.
20/10/03 → 20/08/07