Abstract
A sequence identification apparatus comprising a processor, wherein the apparatus is adapted to access a directed acyclic graph data structure of equivalence classes of events in event sequences identified in a plurality of time-ordered events, and wherein the graph is optimized optimised such that initial and final sub-sequences of event sequences having common equivalence classes are combined in the graph, the apparatus comprising: a code generator adapted to generate executable code corresponding to the graph such that the code includes an instruction sequence for each event classification of the graph, the code sequence for an event classification being adapted to evaluate criteria to determine if an event corresponds to the event classification; a virtual machine adapted to execute the generated executable code such that, in use, the executable code filters incoming time-ordered events based on the graph.
Original language | English |
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Patent number | WO/2015/044630 |
IPC | G06F 9/54 (2006.01), G06F 11/30 (2006.01), G06F 21/55 (2013.01), G06F 9/44 (2006.01) |
Priority date | 26/09/13 |
Publication status | Published - 11 Aug 2016 |