Energy efficient Reconfigurable Computing with Adaptive Voltage and Logic scaling.

Jose L Nunez-Yanez

Research output: Chapter in Book/Report/Conference proceedingConference Contribution (Conference Proceeding)

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This paper investigates a novel energy-proportional concept that combines closed-loop voltage scalability and run-time hardware reconfiguration. Voltage scaling is based on in-situ detectors that allow the device to detect valid working voltage and frequency pairs at run-time. The combined approach named AVLS (Adaptive Voltage and Logic Scaling) enables the adaptation of capacitance, voltage and frequency to obtain power and energy savings based on workload, process and operating conditions in a closed-loop configuration. The technique is applied to a reconfigurable motion estimation processor that can be configured with a variable number of execution units and it is used as a test vehicle. The results demonstrate that the proposed voltage scaling can obtain up to 85% reduction in energy compared with nominal voltage operation at the same frequency. This efficient energy point is obtained at a voltage of 0.62 V and frequency of 56 MHz compared with running the core at the same frequency and nominal 1 V. The addition of logic scalability means that if enough device resources are available a parallel configuration with six execution units operating at 0.62 V reduces energy by up to 95% compared with a single execution unit operating at 1 V and the same frequency.
Original languageEnglish
Title of host publicationACM SIGARCH Computer Architecture News
Subtitle of host publicationHEART '14
EditorsDoug DeGroot
PublisherAssociation for Computing Machinery (ACM)
Number of pages6
Publication statusPublished - 3 Dec 2014

Bibliographical note

ISSN: 0163-5964


  • FPGA
  • energy efficiency
  • DVFS
  • AVS


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