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Energy Optimization in Commercial FPGAs with Voltage, Frequency and Logic Scaling

Research output: Contribution to journalArticle

Original languageEnglish
Pages (from-to)1484-1493
Number of pages10
JournalIEEE Transactions on Computers
Issue number5
Early online date20 May 2015
DateE-pub ahead of print - 20 May 2015
DatePublished (current) - 1 May 2016


This paper investigates the energy reductions possible in commercially available FPGAs configured to support voltage, frequency and logic scalability combined with power gating. Voltage and frequency scaling is based on in-situ detectors that allow the device to detect valid working voltage and frequency pairs at run-time while logic scalability is achieved with partial dynamic reconfiguration. The considered devices are FPGA-processor hybrids with independent power domains fabricated in 28 nm process nodes. The test case is based on a number of operational scenarios in which the FPGA side is loaded with a motion estimation core that can be configured with a variable number of execution units. The results demonstrate that voltage scalability reduces power by up to 60% compared with nominal voltage operation at the same frequency. The energy analysis show that the most energy efficiency core configuration depends on the performance requirements. A low performance scenario shows that serial computation is more energy efficient than the parallel configuration while the opposite is true when the performance requirements increase. An algorithm is proposed to combine effectively adaptive voltage/logic scaling and power gating in the proposed system and application.

    Research areas

  • Clocks, Detectors, Field programmable gate arrays, Monitoring, Motion estimation, Voltage control, Voltage measurement, AVS, DVFS, Energy Optimization, FPGA, Power Gating

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