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Energy Optimization in Commercial FPGAs with Voltage, Frequency and Logic Scaling

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Energy Optimization in Commercial FPGAs with Voltage, Frequency and Logic Scaling. / Nunez-Yanez, Jose L; Hosseinabady, Mohammad; Farhadi Beldachi, Arash F.

In: IEEE Transactions on Computers, Vol. 65, No. 5, 01.05.2016, p. 1484-1493.

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Nunez-Yanez, Jose L ; Hosseinabady, Mohammad ; Farhadi Beldachi, Arash F. / Energy Optimization in Commercial FPGAs with Voltage, Frequency and Logic Scaling. In: IEEE Transactions on Computers. 2016 ; Vol. 65, No. 5. pp. 1484-1493.

Bibtex

@article{da3b6e37e28d464f96d9900722f1ecd5,
title = "Energy Optimization in Commercial FPGAs with Voltage, Frequency and Logic Scaling",
abstract = "This paper investigates the energy reductions possible in commercially available FPGAs configured to support voltage, frequency and logic scalability combined with power gating. Voltage and frequency scaling is based on in-situ detectors that allow the device to detect valid working voltage and frequency pairs at run-time while logic scalability is achieved with partial dynamic reconfiguration. The considered devices are FPGA-processor hybrids with independent power domains fabricated in 28 nm process nodes. The test case is based on a number of operational scenarios in which the FPGA side is loaded with a motion estimation core that can be configured with a variable number of execution units. The results demonstrate that voltage scalability reduces power by up to 60{\%} compared with nominal voltage operation at the same frequency. The energy analysis show that the most energy efficiency core configuration depends on the performance requirements. A low performance scenario shows that serial computation is more energy efficient than the parallel configuration while the opposite is true when the performance requirements increase. An algorithm is proposed to combine effectively adaptive voltage/logic scaling and power gating in the proposed system and application.",
keywords = "Clocks, Detectors, Field programmable gate arrays, Monitoring, Motion estimation, Voltage control, Voltage measurement, AVS, DVFS, Energy Optimization, FPGA, Power Gating",
author = "Nunez-Yanez, {Jose L} and Mohammad Hosseinabady and {Farhadi Beldachi}, {Arash F}",
year = "2016",
month = "5",
day = "1",
doi = "10.1109/TC.2015.2435771",
language = "English",
volume = "65",
pages = "1484--1493",
journal = "IEEE Transactions on Computers",
issn = "0018-9340",
publisher = "IEEE Computer Society",
number = "5",

}

RIS - suitable for import to EndNote

TY - JOUR

T1 - Energy Optimization in Commercial FPGAs with Voltage, Frequency and Logic Scaling

AU - Nunez-Yanez, Jose L

AU - Hosseinabady, Mohammad

AU - Farhadi Beldachi, Arash F

PY - 2016/5/1

Y1 - 2016/5/1

N2 - This paper investigates the energy reductions possible in commercially available FPGAs configured to support voltage, frequency and logic scalability combined with power gating. Voltage and frequency scaling is based on in-situ detectors that allow the device to detect valid working voltage and frequency pairs at run-time while logic scalability is achieved with partial dynamic reconfiguration. The considered devices are FPGA-processor hybrids with independent power domains fabricated in 28 nm process nodes. The test case is based on a number of operational scenarios in which the FPGA side is loaded with a motion estimation core that can be configured with a variable number of execution units. The results demonstrate that voltage scalability reduces power by up to 60% compared with nominal voltage operation at the same frequency. The energy analysis show that the most energy efficiency core configuration depends on the performance requirements. A low performance scenario shows that serial computation is more energy efficient than the parallel configuration while the opposite is true when the performance requirements increase. An algorithm is proposed to combine effectively adaptive voltage/logic scaling and power gating in the proposed system and application.

AB - This paper investigates the energy reductions possible in commercially available FPGAs configured to support voltage, frequency and logic scalability combined with power gating. Voltage and frequency scaling is based on in-situ detectors that allow the device to detect valid working voltage and frequency pairs at run-time while logic scalability is achieved with partial dynamic reconfiguration. The considered devices are FPGA-processor hybrids with independent power domains fabricated in 28 nm process nodes. The test case is based on a number of operational scenarios in which the FPGA side is loaded with a motion estimation core that can be configured with a variable number of execution units. The results demonstrate that voltage scalability reduces power by up to 60% compared with nominal voltage operation at the same frequency. The energy analysis show that the most energy efficiency core configuration depends on the performance requirements. A low performance scenario shows that serial computation is more energy efficient than the parallel configuration while the opposite is true when the performance requirements increase. An algorithm is proposed to combine effectively adaptive voltage/logic scaling and power gating in the proposed system and application.

KW - Clocks

KW - Detectors

KW - Field programmable gate arrays

KW - Monitoring

KW - Motion estimation

KW - Voltage control

KW - Voltage measurement

KW - AVS

KW - DVFS

KW - Energy Optimization

KW - FPGA

KW - Power Gating

U2 - 10.1109/TC.2015.2435771

DO - 10.1109/TC.2015.2435771

M3 - Article

VL - 65

SP - 1484

EP - 1493

JO - IEEE Transactions on Computers

JF - IEEE Transactions on Computers

SN - 0018-9340

IS - 5

ER -