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In this paper, we propose a technique to improve the energy efficiency of FPGA devices by exploiting power gating during idle periods in streaming applications. The main idea is to shuffle idle periods during application execution so that the energy and timing overheads of turning the FPGA on and off can become acceptable. A key requirement is that fast FPGA-based accelerators are available and that the application follows a repetitive nature of execution. In this case, the accelerators work on a successive computing mode to accumulate the idle intervals in different iterations in order to make power gating feasible. Streaming on demand applications which are ubiquitous in embedded and portable devices are very good candidates to benefit from this technique. A case study is presented based on an MP3 player as the streaming application which shows up to 52.9% energy reduction.
|Title of host publication
|2015 25th International Conference on Field Programmable Logic and Applications (FPL 2015)
|Subtitle of host publication
|Proceedings of a meeting held 2-4 September 2015, London, United Kingdom
|Institute of Electrical and Electronics Engineers (IEEE)
|Number of pages
|Published - Dec 2015
|2015 25th International Conference on Field Programmable Logic and Applications (FPL) - Royal Institution, London, United Kingdom
Duration: 2 Sept 2015 → 4 Sept 2015
|2015 25th International Conference on Field Programmable Logic and Applications (FPL)
|2/09/15 → 4/09/15
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- 1 Finished
Nunez-Yanez, J. L.
1/11/13 → 30/04/17