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This paper proposes an architecture inspired by ARM big.LITTLE that combines a hardened host with a cluster of soft processors of different complexities, performance and energy profiles. This coarse-grained FPGA overlay architecture results in a hardware accelerator that offers software like programmability, fast compilation, improved design productivity and application portability. A programming flow based on OpenCL is introduced to allow application programmers to implement parallel algorithms at higher level of abstractions. Current OpenCL tools for FPGAS suffer from long compilation times and limited compiler support. Minor changes to the algorithm normally mean full implementation cycles that can take several hours to complete. The proposed architecture allows changes to the application at run-time with cross-compilation done in the host during program execution. To compensate for the loss of performance compared with custom logic the FPGA cluster supports adaptive voltage scaling that enables higher clock frequencies and better adaptation to the program load. Experimental results demonstrates 70% improvement in computational time and 80% reduction in energy consumption by computing OpenCL kernel on different clusters and various operating voltages and frequencies.
|Title of host publication||Proceedings of the 2nd IEEE NORCAS Conference (NORCAS 2016)|
|Publisher||Institute of Electrical and Electronics Engineers (IEEE)|
|Number of pages||6|
|Publication status||Published - 22 Dec 2016|
|Event||2nd IEEE Nordic Circuits and Systems Conference, NORCAS 2016 - Copenhagen, Denmark|
Duration: 1 Nov 2016 → 2 Nov 2016
|Conference||2nd IEEE Nordic Circuits and Systems Conference, NORCAS 2016|
|Period||1/11/16 → 2/11/16|
- Open CL
- Energy proportional computing
- Soft processors
- Energy profiles
- Hardware accelerator
- Improved design productivity
- Application portability
- Programming flow
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- 1 Finished
Nunez-Yanez, J. L.
5/01/16 → 4/01/20