We present a set of low-cost architectural enhancements to accelerate the execution of certain arithmetic operations common in cryptographic applications on an extensible embedded processor core. The proposed enhancements are generic in the sense that they can be beneficially applied in almost any RISC processor. We implemented the enhancements in form of a cryptographic unit (CU) that offers the programmer an extended instruction set. The CU features a 128-bit wide register file and datapath, which enables it to process 128-bit words and perform 128-bit loads/stores. We analyze the speed-up factors for some arithmetic operations and public-key cryptographic algorithms obtained through these enhancements. In addition, we evaluate the hardware overhead (i.e. silicon area) of integrating the CU into an embedded RISC processor. Our experimental results show that the proposed architectural enhancements allow for a significant performance gain for both RSA and ECC at the expense of an acceptable increase in silicon area. We also demonstrate that the proposed enhancements facilitate the protection of cryptographic algorithms against certain types of side-channel attacks and present an AES implementation hardened against cache-based attacks as a case study.
|Translated title of the contribution||Enhancing an Embedded Processor Core with a Cryptographic Unit for Performance and Security|
|Title of host publication||Reconfigurable Computing and FPGAs - ReConFig 2008|
|Publisher||IEEE Computer Society|
|Publication status||Published - 2008|
Bibliographical noteOther page information: 409-414
Conference Proceedings/Title of Journal: Proceedings of the 4th International Conference on Reconfigurable Computing and FPGAs (ReConFig 2008)
Other identifier: 2000950