This work explores the potential of sharing different arithmetic hardware operators tightly coupled to the integer pipeline of the open-source LEON3 processor. The idea is to map these modules to the same silicon area saving power consumption and area utilisation. The same strategy can be used to extend the architecture of processors optimized for applications with specific energy constraints. The proposed platform serves as a guideline to illustrate gains obtained through partial reconfiguration that need to adapt to changing standards and protocols with a limited number of resources.
|Translated title of the contribution||Evaluating dynamic partial reconfiguration in the integer pipeline of a FPGA-based opensource processor|
|Title of host publication||International Conference on Field Programmable Logic and Applications, 2008 (FPL 2008), Heidelberg|
|Publisher||Institute of Electrical and Electronics Engineers (IEEE)|
|Pages||547 - 550|
|Number of pages||4|
|Publication status||Published - Sep 2008|
|Event||International Conference on Field Programmable Logic and Applications - Prague, Czech Republic|
Duration: 1 Aug 2009 → …
|Conference||International Conference on Field Programmable Logic and Applications|
|Period||1/08/09 → …|
Bibliographical noteRose publication type: Conference contribution
This material is posted here with permission of the IEEE. Such permission of the IEEE does not in any way imply IEEE endorsement of any of the University of Bristol's products or services. Internal or personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution must be obtained from the IEEE by writing to email@example.com.
By choosing to view this document, you agree to all provisions of the copyright laws protecting it.