Evaluating dynamic partial reconfiguration in the integer pipeline of a FPGA-based opensource processor

SIH Zaidi, A Nabina, CN Canagarajah, JL Nunez-Yanez

Research output: Chapter in Book/Report/Conference proceedingConference Contribution (Conference Proceeding)

8 Citations (Scopus)
497 Downloads (Pure)

Abstract

This work explores the potential of sharing different arithmetic hardware operators tightly coupled to the integer pipeline of the open-source LEON3 processor. The idea is to map these modules to the same silicon area saving power consumption and area utilisation. The same strategy can be used to extend the architecture of processors optimized for applications with specific energy constraints. The proposed platform serves as a guideline to illustrate gains obtained through partial reconfiguration that need to adapt to changing standards and protocols with a limited number of resources.
Translated title of the contributionEvaluating dynamic partial reconfiguration in the integer pipeline of a FPGA-based opensource processor
Original languageEnglish
Title of host publicationInternational Conference on Field Programmable Logic and Applications, 2008 (FPL 2008), Heidelberg
PublisherInstitute of Electrical and Electronics Engineers (IEEE)
Pages547 - 550
Number of pages4
ISBN (Print)9781424419609
DOIs
Publication statusPublished - Sep 2008
EventInternational Conference on Field Programmable Logic and Applications - Prague, Czech Republic
Duration: 1 Aug 2009 → …

Conference

ConferenceInternational Conference on Field Programmable Logic and Applications
CountryCzech Republic
CityPrague
Period1/08/09 → …

Bibliographical note

Rose publication type: Conference contribution

Terms of use: Copyright © 2008 IEEE. Reprinted from International Conference on Field Programmable Logic and Applications, 2008 (FPL 2008).


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