Evaluating dynamic partial reconfiguration in the integer pipeline of a FPGA-based opensource processor

SIH Zaidi; A Nabina; CN Canagarajah; JL Nunez-Yanez

doi:10.1109/FPL.2008.4630005

Evaluating dynamic partial reconfiguration in the integer pipeline of a FPGA-based opensource processor

SIH Zaidi, A Nabina, CN Canagarajah, JL Nunez-Yanez

Research output: Chapter in Book/Report/Conference proceeding › Conference Contribution (Conference Proceeding)

8 Citations (Scopus)

686 Downloads (Pure)

Abstract

This work explores the potential of sharing different arithmetic hardware operators tightly coupled to the integer pipeline of the open-source LEON3 processor. The idea is to map these modules to the same silicon area saving power consumption and area utilisation. The same strategy can be used to extend the architecture of processors optimized for applications with specific energy constraints. The proposed platform serves as a guideline to illustrate gains obtained through partial reconfiguration that need to adapt to changing standards and protocols with a limited number of resources.

Translated title of the contribution	Evaluating dynamic partial reconfiguration in the integer pipeline of a FPGA-based opensource processor
Original language	English
Title of host publication	International Conference on Field Programmable Logic and Applications, 2008 (FPL 2008), Heidelberg
Publisher	Institute of Electrical and Electronics Engineers (IEEE)
Pages	547 - 550
Number of pages	4
ISBN (Print)	9781424419609
DOIs	https://doi.org/10.1109/FPL.2008.4630005
Publication status	Published - Sept 2008
Event	International Conference on Field Programmable Logic and Applications - Prague, Czech Republic Duration: 1 Aug 2009 → …

Conference

Conference	International Conference on Field Programmable Logic and Applications
Country/Territory	Czech Republic
City	Prague
Period	1/08/09 → …

Bibliographical note

Rose publication type: Conference contribution

Terms of use: Copyright © 2008 IEEE. Reprinted from International Conference on Field Programmable Logic and Applications, 2008 (FPL 2008).

This material is posted here with permission of the IEEE. Such permission of the IEEE does not in any way imply IEEE endorsement of any of the University of Bristol's products or services. Internal or personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution must be obtained from the IEEE by writing to [email protected].

By choosing to view this document, you agree to all provisions of the copyright laws protecting it.

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Zaidi IEEE FPL 2008Accepted author manuscript, 252 KB

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Zaidi, SIH., Nabina, A., Canagarajah, CN., & Nunez-Yanez, JL. (2008). Evaluating dynamic partial reconfiguration in the integer pipeline of a FPGA-based opensource processor. In International Conference on Field Programmable Logic and Applications, 2008 (FPL 2008), Heidelberg (pp. 547 - 550). Institute of Electrical and Electronics Engineers (IEEE). https://doi.org/10.1109/FPL.2008.4630005

@inproceedings{2514739c226946e1bdf63ada0022ec79,

title = "Evaluating dynamic partial reconfiguration in the integer pipeline of a FPGA-based opensource processor",

abstract = "This work explores the potential of sharing different arithmetic hardware operators tightly coupled to the integer pipeline of the open-source LEON3 processor. The idea is to map these modules to the same silicon area saving power consumption and area utilisation. The same strategy can be used to extend the architecture of processors optimized for applications with specific energy constraints. The proposed platform serves as a guideline to illustrate gains obtained through partial reconfiguration that need to adapt to changing standards and protocols with a limited number of resources.",

author = "SIH Zaidi and A Nabina and CN Canagarajah and JL Nunez-Yanez",

note = "Rose publication type: Conference contribution Terms of use: Copyright {\textcopyright} 2008 IEEE. Reprinted from International Conference on Field Programmable Logic and Applications, 2008 (FPL 2008). This material is posted here with permission of the IEEE. Such permission of the IEEE does not in any way imply IEEE endorsement of any of the University of Bristol's products or services. Internal or personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution must be obtained from the IEEE by writing to [email protected]. By choosing to view this document, you agree to all provisions of the copyright laws protecting it. ; International Conference on Field Programmable Logic and Applications ; Conference date: 01-08-2009",

year = "2008",

month = sep,

doi = "10.1109/FPL.2008.4630005",

language = "English",

isbn = "9781424419609",

pages = "547 -- 550",

booktitle = "International Conference on Field Programmable Logic and Applications, 2008 (FPL 2008), Heidelberg",

publisher = "Institute of Electrical and Electronics Engineers (IEEE)",

address = "United States",

}

Zaidi, SIH, Nabina, A, Canagarajah, CN & Nunez-Yanez, JL 2008, Evaluating dynamic partial reconfiguration in the integer pipeline of a FPGA-based opensource processor. in International Conference on Field Programmable Logic and Applications, 2008 (FPL 2008), Heidelberg. Institute of Electrical and Electronics Engineers (IEEE), pp. 547 - 550, International Conference on Field Programmable Logic and Applications, Prague, Czech Republic, 1/08/09. https://doi.org/10.1109/FPL.2008.4630005

Evaluating dynamic partial reconfiguration in the integer pipeline of a FPGA-based opensource processor. / Zaidi, SIH; Nabina, A; Canagarajah, CN et al.
International Conference on Field Programmable Logic and Applications, 2008 (FPL 2008), Heidelberg. Institute of Electrical and Electronics Engineers (IEEE), 2008. p. 547 - 550.

Research output: Chapter in Book/Report/Conference proceeding › Conference Contribution (Conference Proceeding)

TY - GEN

T1 - Evaluating dynamic partial reconfiguration in the integer pipeline of a FPGA-based opensource processor

AU - Zaidi, SIH

AU - Nabina, A

AU - Canagarajah, CN

AU - Nunez-Yanez, JL

N1 - Rose publication type: Conference contribution Terms of use: Copyright © 2008 IEEE. Reprinted from International Conference on Field Programmable Logic and Applications, 2008 (FPL 2008). This material is posted here with permission of the IEEE. Such permission of the IEEE does not in any way imply IEEE endorsement of any of the University of Bristol's products or services. Internal or personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution must be obtained from the IEEE by writing to [email protected]. By choosing to view this document, you agree to all provisions of the copyright laws protecting it.

PY - 2008/9

Y1 - 2008/9

N2 - This work explores the potential of sharing different arithmetic hardware operators tightly coupled to the integer pipeline of the open-source LEON3 processor. The idea is to map these modules to the same silicon area saving power consumption and area utilisation. The same strategy can be used to extend the architecture of processors optimized for applications with specific energy constraints. The proposed platform serves as a guideline to illustrate gains obtained through partial reconfiguration that need to adapt to changing standards and protocols with a limited number of resources.

AB - This work explores the potential of sharing different arithmetic hardware operators tightly coupled to the integer pipeline of the open-source LEON3 processor. The idea is to map these modules to the same silicon area saving power consumption and area utilisation. The same strategy can be used to extend the architecture of processors optimized for applications with specific energy constraints. The proposed platform serves as a guideline to illustrate gains obtained through partial reconfiguration that need to adapt to changing standards and protocols with a limited number of resources.

U2 - 10.1109/FPL.2008.4630005

DO - 10.1109/FPL.2008.4630005

M3 - Conference Contribution (Conference Proceeding)

SN - 9781424419609

SP - 547

EP - 550

BT - International Conference on Field Programmable Logic and Applications, 2008 (FPL 2008), Heidelberg

PB - Institute of Electrical and Electronics Engineers (IEEE)

T2 - International Conference on Field Programmable Logic and Applications

Y2 - 1 August 2009

ER -

Evaluating dynamic partial reconfiguration in the integer pipeline of a FPGA-based opensource processor

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