Evaluating the Effectiveness of a Vector-Length-Agnostic Instruction Set

Andrei Poenaru*, Simon McIntosh-Smith*

*Corresponding author for this work

Research output: Contribution to conferenceConference Paperpeer-review

4 Citations (Scopus)
203 Downloads (Pure)


In this paper we evaluate the efficacy of the Arm Scalable Vector Extension (SVE) instruction set for HPC workloads using a set of established mini-apps. Exploiting the vector capabilities of SVE will be a key factor in achieving high performance on upcoming generations of Arm-based processors. SVE is a flexible instruction set, but its design is fundamentally different from other contemporary SIMD extensions, such as AVX or NEON, which could present a challenge to its adoption. We use a selection of mini-apps which covers a wide range of scientific application classes to investigate SVE, using a combination of static and dynamic analysis. We inspect how SVE capabilities are used in the mini- apps’ kernels, as generated by all SVE compilers available at the time of writing, for both arithmetic and memory operations. We compare our findings against similar data gathered on currently available processors. Although the extent to which vector code is generated varies by mini- app, all compilers tested successfully utilise SVE to vectorise more code than they are able to when targeting NEON, Arm’s previous-generation SIMD instruction set. For most mini-apps, we expect performance im- provements as SVE width is increased.
Original languageEnglish
Number of pages16
Publication statusE-pub ahead of print - 18 Aug 2020
EventEuro-Par: 26th International European Conference on Parallel and Distributed Computing - Online, Warsaw, Poland
Duration: 24 Aug 202028 Aug 2020


ConferenceEuro-Par: 26th International European Conference on Parallel and Distributed Computing
Abbreviated titleEuro-Par 2020
Internet address


  • Instruction sets
  • SVE
  • Vectorisation
  • SIMD
  • Data Parallelism


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