Exploiting Emergence in On-chip Interconnects

To solve the grand challenges in contemporary chip design,
such as process-to-core mapping, energy reduction and maintenance
of programmer/hardware abstraction, we advocate for self-optimising
(emergent) Networks-on-Chip (NoC). In these networks, topology and
information flow adapt dynamically to maximise the network throughput
or minimise the network latency via distributed application of micro-rules.

In this paper, we introduce the concept of emergent small-world
NoCs and discuss novel design decisions, e.g. Skip-links, that improve
performance and reduce energy consumption of multi-core systems.
More precisely, we demonstrate that our proposed solution is able to
adapt to a wide range of traffic patterns and provide reductions in data
hop count of up to 20% whilst maintaining energy and area costs.

We show how emergent networks can be useful for on-chip processor-
to-processor communications, and also demonstrate how SoC and off-
chip I/O traffic may be optimised for latency and critical load.