Exploiting Emergence in On-chip Interconnects

Mathematics

• Interconnect 100%
• Chip 86%
• Latency 58%
• Traffic 49%
• Network on chip 44%
• System-on-chip 43%
• Distributed Applications 38%
• Energy Consumption 34%
• Critical Load 32%
• Energy 30%
• Network Topology 29%
• Design 27%
• Hardware 27%
• Demonstrate 26%
• Abstraction 24%
• Maximise 21%
• Communication 20%
• Count 19%
• Minimise 17%
• Costs 16%
• Range of data 13%
• Concepts 11%

Engineering & Materials Science

• Network-on-chip 37%
• System-on-chip 34%
• Energy utilization 23%
• Topology 22%
• Computer hardware 19%
• Communication 16%
• Costs 12%